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https://github.com/brain-hackers/u-boot-brain
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984618f3e7
This patch is in preparation of additional changes to the sysace driver. May as well take this opportunity to fixup the inconsistent whitespace since this file is about to undergo major changes anyway. There are zero functional changes in this patch. It only cleans up the the whitespace. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
265 lines
6.8 KiB
C
265 lines
6.8 KiB
C
/*
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* Copyright (c) 2004 Picture Elements, Inc.
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* Stephen Williams (XXXXXXXXXXXXXXXX)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* The Xilinx SystemACE chip support is activated by defining
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* CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
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* to set the base address of the device. This code currently
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* assumes that the chip is connected via a byte-wide bus.
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*
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* The CONFIG_SYSTEMACE also adds to fat support the device class
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* "ace" that allows the user to execute "fatls ace 0" and the
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* like. This works by making the systemace_get_dev function
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* available to cmd_fat.c:get_dev and filling in a block device
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* description that has all the bits needed for FAT support to
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* read sectors.
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*
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* According to Xilinx technical support, before accessing the
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* SystemACE CF you need to set the following control bits:
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* FORCECFGMODE : 1
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* CFGMODE : 0
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* CFGSTART : 0
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*/
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#include <common.h>
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#include <command.h>
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#include <systemace.h>
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#include <part.h>
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#include <asm/io.h>
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#ifdef CONFIG_SYSTEMACE
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/*
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* The ace_readw and writew functions read/write 16bit words, but the
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* offset value is the BYTE offset as most used in the Xilinx
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* datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
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* to be the base address for the chip, usually in the local
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* peripheral bus.
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*/
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static unsigned ace_readw(unsigned offset)
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{
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#if (CFG_SYSTEMACE_WIDTH == 8)
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u16 temp;
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#if !defined(__BIG_ENDIAN)
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temp = ((u16) readb(CFG_SYSTEMACE_BASE + offset) << 8);
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temp |= (u16) readb(CFG_SYSTEMACE_BASE + offset + 1);
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#else
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temp = (u16) readb(CFG_SYSTEMACE_BASE + offset);
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temp |= ((u16) readb(CFG_SYSTEMACE_BASE + offset + 1) << 8);
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#endif
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return temp;
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#else
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return readw(CFG_SYSTEMACE_BASE + offset);
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#endif
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}
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static void ace_writew(unsigned val, unsigned offset)
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{
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#if (CFG_SYSTEMACE_WIDTH == 8)
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#if !defined(__BIG_ENDIAN)
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writeb((u8) (val >> 8), CFG_SYSTEMACE_BASE + offset);
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writeb((u8) val, CFG_SYSTEMACE_BASE + offset + 1);
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#else
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writeb((u8) val, CFG_SYSTEMACE_BASE + offset);
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writeb((u8) (val >> 8), CFG_SYSTEMACE_BASE + offset + 1);
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#endif
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#else
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writew(val, CFG_SYSTEMACE_BASE + offset);
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#endif
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}
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/* */
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static unsigned long systemace_read(int dev, unsigned long start,
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unsigned long blkcnt,
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unsigned long *buffer);
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static block_dev_desc_t systemace_dev = { 0 };
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static int get_cf_lock(void)
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{
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int retry = 10;
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/* CONTROLREG = LOCKREG */
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unsigned val = ace_readw(0x18);
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val |= 0x0002;
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ace_writew((val & 0xffff), 0x18);
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/* Wait for MPULOCK in STATUSREG[15:0] */
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while (!(ace_readw(0x04) & 0x0002)) {
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if (retry < 0)
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return -1;
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udelay(100000);
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retry -= 1;
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}
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return 0;
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}
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static void release_cf_lock(void)
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{
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unsigned val = ace_readw(0x18);
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val &= ~(0x0002);
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ace_writew((val & 0xffff), 0x18);
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}
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block_dev_desc_t *systemace_get_dev(int dev)
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{
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/* The first time through this, the systemace_dev object is
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not yet initialized. In that case, fill it in. */
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if (systemace_dev.blksz == 0) {
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systemace_dev.if_type = IF_TYPE_UNKNOWN;
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systemace_dev.dev = 0;
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systemace_dev.part_type = PART_TYPE_UNKNOWN;
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systemace_dev.type = DEV_TYPE_HARDDISK;
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systemace_dev.blksz = 512;
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systemace_dev.removable = 1;
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systemace_dev.block_read = systemace_read;
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init_part(&systemace_dev);
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}
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return &systemace_dev;
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}
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/*
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* This function is called (by dereferencing the block_read pointer in
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* the dev_desc) to read blocks of data. The return value is the
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* number of blocks read. A zero return indicates an error.
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*/
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static unsigned long systemace_read(int dev, unsigned long start,
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unsigned long blkcnt, unsigned long *buffer)
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{
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int retry;
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unsigned blk_countdown;
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unsigned char *dp = (unsigned char *)buffer;
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unsigned val;
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if (get_cf_lock() < 0) {
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unsigned status = ace_readw(0x04);
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/* If CFDETECT is false, card is missing. */
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if (!(status & 0x0010)) {
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printf("** CompactFlash card not present. **\n");
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return 0;
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}
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printf("**** ACE locked away from me (STATUSREG=%04x)\n",
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status);
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return 0;
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}
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#ifdef DEBUG_SYSTEMACE
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printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
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#endif
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retry = 2000;
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for (;;) {
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val = ace_readw(0x04);
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/* If CFDETECT is false, card is missing. */
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if (!(val & 0x0010)) {
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printf("**** ACE CompactFlash not found.\n");
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release_cf_lock();
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return 0;
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}
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/* If RDYFORCMD, then we are ready to go. */
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if (val & 0x0100)
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break;
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if (retry < 0) {
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printf("**** SystemACE not ready.\n");
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release_cf_lock();
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return 0;
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}
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udelay(1000);
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retry -= 1;
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}
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/* The SystemACE can only transfer 256 sectors at a time, so
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limit the current chunk of sectors. The blk_countdown
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variable is the number of sectors left to transfer. */
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blk_countdown = blkcnt;
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while (blk_countdown > 0) {
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unsigned trans = blk_countdown;
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if (trans > 256)
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trans = 256;
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#ifdef DEBUG_SYSTEMACE
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printf("... transfer %lu sector in a chunk\n", trans);
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#endif
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/* Write LBA block address */
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ace_writew((start >> 0) & 0xffff, 0x10);
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ace_writew((start >> 16) & 0x00ff, 0x12);
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/* NOTE: in the Write Sector count below, a count of 0
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causes a transfer of 256, so &0xff gives the right
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value for whatever transfer count we want. */
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/* Write sector count | ReadMemCardData. */
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ace_writew((trans & 0xff) | 0x0300, 0x14);
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/* Reset the configruation controller */
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val = ace_readw(0x18);
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val |= 0x0080;
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ace_writew(val, 0x18);
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retry = trans * 16;
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while (retry > 0) {
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int idx;
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/* Wait for buffer to become ready. */
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while (!(ace_readw(0x04) & 0x0020)) {
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udelay(100);
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}
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/* Read 16 words of 2bytes from the sector buffer. */
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for (idx = 0; idx < 16; idx += 1) {
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unsigned short val = ace_readw(0x40);
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*dp++ = val & 0xff;
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*dp++ = (val >> 8) & 0xff;
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}
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retry -= 1;
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}
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/* Clear the configruation controller reset */
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val = ace_readw(0x18);
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val &= ~0x0080;
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ace_writew(val, 0x18);
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/* Count the blocks we transfer this time. */
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start += trans;
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blk_countdown -= trans;
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}
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release_cf_lock();
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return blkcnt;
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}
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#endif /* CONFIG_SYSTEMACE */
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