mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-30 06:43:45 +09:00
983e37007d
This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories. All refernces to the former locations are updated to
the current locations. For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.
Signed-off-by: Tom Rini <trini@konsulko.com>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
/*
|
|
* This file configures the internal USB PHY in AM35X.
|
|
*
|
|
* Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
|
|
*
|
|
* Based on omap_phy_internal.c code from Linux by
|
|
* Hema HK <hemahk@ti.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/am35x_def.h>
|
|
|
|
void am35x_musb_reset(void)
|
|
{
|
|
/* Reset the musb interface */
|
|
clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
|
|
0, USBOTGSS_SW_RST);
|
|
clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
|
|
USBOTGSS_SW_RST, 0);
|
|
}
|
|
|
|
void am35x_musb_phy_power(u8 on)
|
|
{
|
|
unsigned long start = get_timer(0);
|
|
|
|
if (on) {
|
|
/*
|
|
* Start the on-chip PHY and its PLL.
|
|
*/
|
|
clrsetbits_le32(&am35x_scm_general_regs->devconf2,
|
|
CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
|
|
CONF2_PHY_PLLON);
|
|
|
|
debug("Waiting for PHY clock good...\n");
|
|
while (!(readl(&am35x_scm_general_regs->devconf2)
|
|
& CONF2_PHYCLKGD)) {
|
|
|
|
if (get_timer(start) > CONFIG_SYS_HZ / 10) {
|
|
printf("musb PHY clock good timed out\n");
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
/*
|
|
* Power down the on-chip PHY.
|
|
*/
|
|
clrsetbits_le32(&am35x_scm_general_regs->devconf2,
|
|
CONF2_PHY_PLLON,
|
|
CONF2_PHYPWRDN | CONF2_OTGPWRDN);
|
|
}
|
|
}
|
|
|
|
void am35x_musb_clear_irq(void)
|
|
{
|
|
clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
|
|
0, USBOTGSS_INT_CLR);
|
|
readl(&am35x_scm_general_regs->lvl_intr_clr);
|
|
}
|