mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
552a848e4f
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
108 lines
2.9 KiB
C
108 lines
2.9 KiB
C
/*
|
|
* Copyright 2015 Freescale Semiconductor, Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/armv7.h>
|
|
#include <asm/pl310.h>
|
|
#include <asm/io.h>
|
|
#include <asm/mach-imx/sys_proto.h>
|
|
|
|
#ifndef CONFIG_SYS_DCACHE_OFF
|
|
void enable_caches(void)
|
|
{
|
|
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
|
|
enum dcache_option option = DCACHE_WRITETHROUGH;
|
|
#else
|
|
enum dcache_option option = DCACHE_WRITEBACK;
|
|
#endif
|
|
/* Avoid random hang when download by usb */
|
|
invalidate_dcache_all();
|
|
|
|
/* Enable D-cache. I-cache is already enabled in start.S */
|
|
dcache_enable();
|
|
|
|
/* Enable caching on OCRAM and ROM */
|
|
mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
|
|
ROMCP_ARB_END_ADDR,
|
|
option);
|
|
mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
|
|
IRAM_SIZE,
|
|
option);
|
|
}
|
|
#endif
|
|
|
|
#ifndef CONFIG_SYS_L2CACHE_OFF
|
|
#ifdef CONFIG_SYS_L2_PL310
|
|
#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
|
|
void v7_outer_cache_enable(void)
|
|
{
|
|
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
|
|
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
unsigned int val;
|
|
|
|
|
|
/*
|
|
* Must disable the L2 before changing the latency parameters
|
|
* and auxiliary control register.
|
|
*/
|
|
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
|
|
|
|
/*
|
|
* Set bit 22 in the auxiliary control register. If this bit
|
|
* is cleared, PL310 treats Normal Shared Non-cacheable
|
|
* accesses as Cacheable no-allocate.
|
|
*/
|
|
setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
|
|
|
|
if (is_mx6sl() || is_mx6sll()) {
|
|
val = readl(&iomux->gpr[11]);
|
|
if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
|
|
/* L2 cache configured as OCRAM, reset it */
|
|
val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
|
|
writel(val, &iomux->gpr[11]);
|
|
}
|
|
}
|
|
|
|
writel(0x132, &pl310->pl310_tag_latency_ctrl);
|
|
writel(0x132, &pl310->pl310_data_latency_ctrl);
|
|
|
|
val = readl(&pl310->pl310_prefetch_ctrl);
|
|
|
|
/* Turn on the L2 I/D prefetch */
|
|
val |= 0x30000000;
|
|
|
|
/*
|
|
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
|
|
* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
|
|
* But according to ARM PL310 errata: 752271
|
|
* ID: 752271: Double linefill feature can cause data corruption
|
|
* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
|
|
* Workaround: The only workaround to this erratum is to disable the
|
|
* double linefill feature. This is the default behavior.
|
|
*/
|
|
|
|
#ifndef CONFIG_MX6Q
|
|
val |= 0x40800000;
|
|
#endif
|
|
writel(val, &pl310->pl310_prefetch_ctrl);
|
|
|
|
val = readl(&pl310->pl310_power_ctrl);
|
|
val |= L2X0_DYNAMIC_CLK_GATING_EN;
|
|
val |= L2X0_STNDBY_MODE_EN;
|
|
writel(val, &pl310->pl310_power_ctrl);
|
|
|
|
setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
|
|
}
|
|
|
|
void v7_outer_cache_disable(void)
|
|
{
|
|
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
|
|
|
|
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
|
|
}
|
|
#endif /* !CONFIG_SYS_L2_PL310 */
|
|
#endif /* !CONFIG_SYS_L2CACHE_OFF */
|