mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 04:36:16 +09:00
660d5f0d49
"reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU. This change is a preparation to submission of ARCv2 architecture port. Even though ARCv1 and ARCv2 ISAs are not binary compatible most of built-in modules still have the same programming model - AUX registers are mapped in the same addresses and hold the same data (new featues extend existing ones). So only low-level assembly code (start-up, interrupt handlers) is left as CPU(actually ISA)-specific. This significantyl simplifies maintenance of multiple CPUs/ISAs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
25 lines
553 B
C
25 lines
553 B
C
/*
|
|
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <asm/arcregs.h>
|
|
|
|
#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */
|
|
|
|
int timer_init(void)
|
|
{
|
|
write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
|
|
/* Set max value for counter/timer */
|
|
write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
|
|
/* Set initial count value and restart counter/timer */
|
|
write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
|
|
return 0;
|
|
}
|
|
|
|
unsigned long timer_read_counter(void)
|
|
{
|
|
return read_aux_reg(ARC_AUX_TIMER0_CNT);
|
|
}
|