mirror of
https://github.com/brain-hackers/u-boot-brain
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181 lines
4.6 KiB
C
181 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*/
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/intel_regs.h>
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#include <asm/pci.h>
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#include <asm/arch/systemagent.h>
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/**
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* struct apl_hostbridge_platdata - platform data for hostbridge
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*
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* @dtplat: Platform data for of-platdata
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* @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
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* @early_pads_count: Number of pads to process
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* @pciex_region_size: BAR length in bytes
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* @bdf: Bus/device/function of hostbridge
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*/
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struct apl_hostbridge_platdata {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_intel_apl_hostbridge dtplat;
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#endif
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u32 *early_pads;
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int early_pads_count;
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uint pciex_region_size;
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pci_dev_t bdf;
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};
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enum {
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PCIEXBAR = 0x60,
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PCIEXBAR_LENGTH_256MB = 0,
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PCIEXBAR_LENGTH_128MB,
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PCIEXBAR_LENGTH_64MB,
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PCIEXBAR_PCIEXBAREN = 1 << 0,
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TSEG = 0xb8, /* TSEG base */
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};
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static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
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{
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struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
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struct udevice *pinctrl;
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int ret;
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ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
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if (ret)
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return log_msg_ret("no hostbridge pinctrl", ret);
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return pinctrl_config_pads(pinctrl, plat->early_pads,
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plat->early_pads_count);
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}
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static int apl_hostbridge_early_init(struct udevice *dev)
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{
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struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
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u32 region_size;
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ulong base;
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u32 reg;
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int ret;
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/* Set up the MCHBAR */
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pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32);
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base = MCH_BASE_ADDRESS;
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pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32);
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/*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB
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*/
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pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32);
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switch (plat->pciex_region_size >> 20) {
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default:
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case 256:
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region_size = PCIEXBAR_LENGTH_256MB;
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break;
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case 128:
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region_size = PCIEXBAR_LENGTH_128MB;
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break;
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case 64:
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region_size = PCIEXBAR_LENGTH_64MB;
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break;
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}
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reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1)
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| PCIEXBAR_PCIEXBAREN;
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pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32);
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/*
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* TSEG defines the base of SMM range. BIOS determines the base
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* of TSEG memory which must be at or below Graphics base of GTT
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* Stolen memory, hence its better to clear TSEG register early
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* to avoid power on default non-zero value (if any).
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*/
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pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32);
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ret = apl_hostbridge_early_init_pinctrl(dev);
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if (ret)
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return log_msg_ret("pinctrl", ret);
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return 0;
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}
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static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
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{
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struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
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struct udevice *pinctrl;
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int ret;
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/*
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* The host bridge holds the early pad data needed to get through TPL.
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* This is a small amount of data, enough to fit in TPL, so we keep it
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* separate from the full pad data, stored in the fsp-s subnode. That
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* subnode is not present in TPL, to save space.
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*/
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ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
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if (ret)
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return log_msg_ret("no hostbridge PINCTRL", ret);
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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int root;
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/* Get length of PCI Express Region */
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plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size",
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256 << 20);
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root = pci_get_devfn(dev);
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if (root < 0)
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return log_msg_ret("Cannot get host-bridge PCI address", root);
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plat->bdf = root;
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ret = pinctrl_read_pads(pinctrl, dev_ofnode(dev), "early-pads",
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&plat->early_pads, &plat->early_pads_count);
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if (ret)
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return log_msg_ret("early-pads", ret);
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#else
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struct dtd_intel_apl_hostbridge *dtplat = &plat->dtplat;
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int size;
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plat->pciex_region_size = dtplat->pciex_region_size;
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plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
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/* Assume that if everything is 0, it is empty */
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plat->early_pads = dtplat->early_pads;
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size = ARRAY_SIZE(dtplat->early_pads);
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plat->early_pads_count = pinctrl_count_pads(pinctrl, plat->early_pads,
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size);
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#endif
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return 0;
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}
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static int apl_hostbridge_probe(struct udevice *dev)
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{
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if (spl_phase() == PHASE_TPL)
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return apl_hostbridge_early_init(dev);
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return 0;
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}
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static const struct udevice_id apl_hostbridge_ids[] = {
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{ .compatible = "intel,apl-hostbridge" },
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{ }
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};
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U_BOOT_DRIVER(apl_hostbridge_drv) = {
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.name = "intel_apl_hostbridge",
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.id = UCLASS_NORTHBRIDGE,
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.of_match = apl_hostbridge_ids,
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.ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata,
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.probe = apl_hostbridge_probe,
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.platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata),
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};
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