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![]() To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> |
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.. | ||
base_addr_a10.h | ||
base_addr_ac5.h | ||
clock_manager.h | ||
fpga_manager.h | ||
freeze_controller.h | ||
gpio.h | ||
nic301.h | ||
reset_manager.h | ||
scan_manager.h | ||
scu.h | ||
sdram.h | ||
system_manager.h | ||
timer.h |