mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 07:06:19 +09:00
0f1fa36fff
T104xrdb has several sleep management signals that are used for deep sleep. They are enabled by OS to enter deep sleep and should be disabled by u-boot when cores wake up. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
119 lines
2.3 KiB
C
119 lines
2.3 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include <asm/mpc85xx_gpio.h>
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#include "t104xrdb.h"
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#include "cpld.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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struct cpu_type *cpu = gd->arch.cpu;
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u8 sw;
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printf("Board: %sRDB\n", cpu->name);
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printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
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CPLD_READ(hw_ver), CPLD_READ(sw_ver));
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sw = CPLD_READ(flash_ctl_status);
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sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
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if (sw <= 7)
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printf("vBank: %d\n", sw);
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else
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printf("Unsupported Bank=%x\n", sw);
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_SYS_FLASH_BASE
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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#endif
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set_liodns();
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#ifdef CONFIG_SYS_DPAA_QBMAN
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setup_portals();
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#endif
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return 0;
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}
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int misc_init_r(void)
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{
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return 0;
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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#ifdef CONFIG_HAS_FSL_DR_USB
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fdt_fixup_dr_usb(blob, bd);
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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#endif
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}
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#ifdef CONFIG_DEEP_SLEEP
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void board_mem_sleep_setup(void)
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{
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/* does not provide HW signals for power management */
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CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
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/* Disable MCKE isolation */
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gpio_set_value(2, 0);
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udelay(1);
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}
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#endif
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