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https://github.com/brain-hackers/u-boot-brain
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3119ecc4ac
This is workaround for issue we can't get correct size for 4GB ram in 32bit system and available before we really need ram space out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram). The size of 4GB is '0x1 00000000', and this value will be truncated to 0 in 32bit system, and system can not get correct ram size. Rockchip SoCs reserve a blob of space for peripheral near 4GB, and we are now setting SDRAM_MAX_SIZE as max available space for ram in 4GB, so we can use this directly to workaround the issue. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-By: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <dm.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/arch/sdram_common.h>
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#include <dm/uclass-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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size_t rockchip_sdram_size(phys_addr_t reg)
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{
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u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
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size_t chipsize_mb = 0;
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size_t size_mb = 0;
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u32 ch;
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u32 sys_reg = readl(reg);
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u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
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& SYS_REG_NUM_CH_MASK);
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debug("%s %x %x\n", __func__, (u32)reg, sys_reg);
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for (ch = 0; ch < ch_num; ch++) {
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rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
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SYS_REG_RANK_MASK);
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col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
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bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
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cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
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SYS_REG_CS0_ROW_MASK);
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cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
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SYS_REG_CS1_ROW_MASK);
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bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
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SYS_REG_BW_MASK));
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row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
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SYS_REG_ROW_3_4_MASK;
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chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
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if (rank > 1)
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chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
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if (row_3_4)
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chipsize_mb = chipsize_mb * 3 / 4;
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size_mb += chipsize_mb;
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debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
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rank, col, bk, cs0_row, bw, row_3_4);
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}
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/*
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* This is workaround for issue we can't get correct size for 4GB ram
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* in 32bit system and available before we really need ram space
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* out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
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* The size of 4GB is '0x1 00000000', and this value will be truncated
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* to 0 in 32bit system, and system can not get correct ram size.
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* Rockchip SoCs reserve a blob of space for peripheral near 4GB,
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* and we are now setting SDRAM_MAX_SIZE as max available space for
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* ram in 4GB, so we can use this directly to workaround the issue.
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* TODO:
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* 1. update correct value for SDRAM_MAX_SIZE as what dram
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* controller sees.
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* 2. update board_get_usable_ram_top() and dram_init_banksize()
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* to reserve memory for peripheral space after previous update.
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*/
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if (size_mb > (SDRAM_MAX_SIZE >> 20))
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size_mb = (SDRAM_MAX_SIZE >> 20);
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return (size_t)size_mb << 20;
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}
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int dram_init(void)
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{
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struct ram_info ram;
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struct udevice *dev;
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int ret;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return ret;
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}
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ret = ram_get_info(dev, &ram);
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if (ret) {
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debug("Cannot get DRAM size: %d\n", ret);
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return ret;
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}
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gd->ram_size = ram.size;
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debug("SDRAM base=%lx, size=%lx\n",
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(unsigned long)ram.base, (unsigned long)ram.size);
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return 0;
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}
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ulong board_get_usable_ram_top(ulong total_size)
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{
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unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
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return (gd->ram_top > top) ? top : gd->ram_top;
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}
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