Fabio Estevam 9691c5b96d mx53: ddr3: Update DD3 initialization ... Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>		2011-09-04 11:36:11 +02:00
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imximage_dd3.cfg	mx53: ddr3: Update DD3 initialization	2011-09-04 11:36:11 +02:00
Makefile	MX53: Add initial support for MX53ARD	2011-07-04 10:55:26 +02:00
mx53ard.c	Remove volatile qualifier in get_ram_size() calls	2011-07-17 17:11:53 +02:00