mirror of
https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
223 lines
5.7 KiB
C
223 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <image.h>
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#include <asm/arch/reset_manager.h>
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#include <spl.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/freeze_controller.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/scu.h>
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#include <asm/arch/nic301.h>
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#include <asm/sections.h>
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#include <fdtdec.h>
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#include <watchdog.h>
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#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#include <asm/arch/pinmux.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static struct scu_registers *scu_regs =
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(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
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static struct nic301_registers *nic301_regs =
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(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
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#endif
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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u32 spl_boot_device(void)
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{
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const u32 bsel = readl(&sysmgr_regs->bootinfo);
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switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
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case 0x1: /* FPGA (HPS2FPGA Bridge) */
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return BOOT_DEVICE_RAM;
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case 0x2: /* NAND Flash (1.8V) */
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case 0x3: /* NAND Flash (3.0V) */
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socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
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return BOOT_DEVICE_NAND;
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case 0x4: /* SD/MMC External Transceiver (1.8V) */
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case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
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socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
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socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
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return BOOT_DEVICE_MMC1;
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case 0x6: /* QSPI Flash (1.8V) */
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case 0x7: /* QSPI Flash (3.0V) */
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socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
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return BOOT_DEVICE_SPI;
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default:
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printf("Invalid boot device (bsel=%08x)!\n", bsel);
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hang();
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}
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}
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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static void socfpga_nic301_slave_ns(void)
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{
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writel(0x1, &nic301_regs->lwhps2fpgaregs);
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writel(0x1, &nic301_regs->hps2fpgaregs);
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writel(0x1, &nic301_regs->acp);
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writel(0x1, &nic301_regs->rom);
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writel(0x1, &nic301_regs->ocram);
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writel(0x1, &nic301_regs->sdrdata);
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}
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void board_init_f(ulong dummy)
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{
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#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
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const struct cm_config *cm_default_cfg = cm_get_default_config();
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#endif
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unsigned long sdram_size;
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unsigned long reg;
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/*
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* First C code to run. Clear fake OCRAM ECC first as SBE
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* and DBE might triggered during power on
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*/
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reg = readl(&sysmgr_regs->eccgrp_ocram);
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if (reg & SYSMGR_ECC_OCRAM_SERR)
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writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
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&sysmgr_regs->eccgrp_ocram);
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if (reg & SYSMGR_ECC_OCRAM_DERR)
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writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
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&sysmgr_regs->eccgrp_ocram);
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memset(__bss_start, 0, __bss_end - __bss_start);
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socfpga_nic301_slave_ns();
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/* Configure ARM MPU SNSAC register. */
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setbits_le32(&scu_regs->sacr, 0xfff);
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/* Remap SDRAM to 0x0 */
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writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
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writel(0x1, &pl310->pl310_addr_filter_start);
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#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
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debug("Freezing all I/O banks\n");
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/* freeze all IO banks */
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sys_mgr_frzctrl_freeze_req();
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/* Put everything into reset but L4WD0. */
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socfpga_per_reset_all();
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/* Put FPGA bridges into reset too. */
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socfpga_bridges_reset(1);
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socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
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socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
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socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
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timer_init();
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debug("Reconfigure Clock Manager\n");
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/* reconfigure the PLLs */
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if (cm_basic_init(cm_default_cfg))
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hang();
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/* Enable bootrom to configure IOs. */
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sysmgr_config_warmrstcfgio(1);
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/* configure the IOCSR / IO buffer settings */
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if (scan_mgr_configure_iocsr())
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hang();
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sysmgr_config_warmrstcfgio(0);
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/* configure the pin muxing through system manager */
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sysmgr_config_warmrstcfgio(1);
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sysmgr_pinmux_init();
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sysmgr_config_warmrstcfgio(0);
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#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
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/* De-assert reset for peripherals and bridges based on handoff */
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reset_deassert_peripherals_handoff();
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socfpga_bridges_reset(0);
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debug("Unfreezing/Thaw all I/O banks\n");
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/* unfreeze / thaw all IO banks */
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sys_mgr_frzctrl_thaw_req();
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/* enable console uart printing */
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preloader_console_init();
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if (sdram_mmr_init_full(0xffffffff) != 0) {
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puts("SDRAM init failed.\n");
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hang();
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}
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debug("SDRAM: Calibrating PHY\n");
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/* SDRAM calibration */
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if (sdram_calibration_full() == 0) {
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puts("SDRAM calibration failed.\n");
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hang();
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}
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sdram_size = sdram_calculate_size();
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debug("SDRAM: %ld MiB\n", sdram_size >> 20);
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/* Sanity check ensure correct SDRAM size specified */
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if (get_ram_size(0, sdram_size) != sdram_size) {
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puts("SDRAM size check failed!\n");
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hang();
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}
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socfpga_bridges_reset(1);
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/* Configure simple malloc base pointer into RAM. */
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gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
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}
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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void spl_board_init(void)
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{
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/* configuring the clock based on handoff */
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cm_basic_init(gd->fdt_blob);
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WATCHDOG_RESET();
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config_dedicated_pins(gd->fdt_blob);
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WATCHDOG_RESET();
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/* Release UART from reset */
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socfpga_reset_uart(0);
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/* enable console uart printing */
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preloader_console_init();
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}
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void board_init_f(ulong dummy)
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{
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/*
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* Configure Clock Manager to use intosc clock instead external osc to
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* ensure success watchdog operation. We do it as early as possible.
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*/
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cm_use_intosc();
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socfpga_watchdog_disable();
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arch_early_init_r();
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#ifdef CONFIG_HW_WATCHDOG
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/* release osc1 watchdog timer 0 from reset */
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socfpga_reset_deassert_osc1wd0();
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/* reconfigure and enable the watchdog */
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hw_watchdog_init();
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WATCHDOG_RESET();
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#endif /* CONFIG_HW_WATCHDOG */
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}
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#endif
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