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https://github.com/brain-hackers/u-boot-brain
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d3a22419cf
The infomation of module control register for R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) are almost the same, they can be combined into one structure. This provides structure that summarizes infomation of module control register and default register values. And this structure is the module control use of the kernel at boot time. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
110 lines
2.5 KiB
C
110 lines
2.5 KiB
C
/*
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* arch/arm/include/asm/arch-rmobile/rcar-mstp.h
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*
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* Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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* Copyright (C) 2013, 2014 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ASM_ARCH_RCAR_MSTP_H
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#define __ASM_ARCH_RCAR_MSTP_H
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#define mstp_setbits(type, addr, saddr, set) \
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out_##type((saddr), in_##type(addr) | (set))
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#define mstp_clrbits(type, addr, saddr, clear) \
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out_##type((saddr), in_##type(addr) & ~(clear))
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#define mstp_setclrbits(type, addr, set, clear) \
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out_##type((addr), (in_##type(addr) | (set)) & ~(clear))
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#define mstp_setbits_le32(addr, saddr, set) \
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mstp_setbits(le32, addr, saddr, set)
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#define mstp_clrbits_le32(addr, saddr, clear) \
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mstp_clrbits(le32, addr, saddr, clear)
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#define mstp_setclrbits_le32(addr, set, clear) \
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mstp_setclrbits(le32, addr, set, clear)
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#ifndef CONFIG_SMSTP0_ENA
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#define CONFIG_SMSTP0_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP1_ENA
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#define CONFIG_SMSTP1_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP2_ENA
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#define CONFIG_SMSTP2_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP3_ENA
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#define CONFIG_SMSTP3_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP4_ENA
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#define CONFIG_SMSTP4_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP5_ENA
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#define CONFIG_SMSTP5_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP6_ENA
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#define CONFIG_SMSTP6_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP7_ENA
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#define CONFIG_SMSTP7_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP8_ENA
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#define CONFIG_SMSTP8_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP9_ENA
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#define CONFIG_SMSTP9_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP10_ENA
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#define CONFIG_SMSTP10_ENA 0x00
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#endif
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#ifndef CONFIG_SMSTP11_ENA
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#define CONFIG_SMSTP11_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP0_ENA
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#define CONFIG_RMSTP0_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP1_ENA
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#define CONFIG_RMSTP1_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP2_ENA
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#define CONFIG_RMSTP2_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP3_ENA
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#define CONFIG_RMSTP3_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP4_ENA
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#define CONFIG_RMSTP4_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP5_ENA
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#define CONFIG_RMSTP5_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP6_ENA
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#define CONFIG_RMSTP6_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP7_ENA
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#define CONFIG_RMSTP7_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP8_ENA
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#define CONFIG_RMSTP8_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP9_ENA
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#define CONFIG_RMSTP9_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP10_ENA
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#define CONFIG_RMSTP10_ENA 0x00
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#endif
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#ifndef CONFIG_RMSTP11_ENA
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#define CONFIG_RMSTP11_ENA 0x00
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#endif
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struct mstp_ctl {
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u32 s_addr;
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u32 s_dis;
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u32 s_ena;
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u32 r_addr;
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u32 r_dis;
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u32 r_ena;
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};
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#endif /* __ASM_ARCH_RCAR_MSTP_H */
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