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https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
226 lines
7.9 KiB
C
226 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Header file for AT91/AT32 MULTI LAYER LCD Controller
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*
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* Data structure and register user interface
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*
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* Copyright (C) 2012 Atmel Corporation
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*/
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#ifndef __ATMEL_HLCDC_H__
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#define __ATMEL_HLCDC_H__
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/* Atmel multi layer lcdc hardware registers */
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struct atmel_hlcd_regs {
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u32 lcdc_lcdcfg0;
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u32 lcdc_lcdcfg1;
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u32 lcdc_lcdcfg2;
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u32 lcdc_lcdcfg3;
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u32 lcdc_lcdcfg4;
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u32 lcdc_lcdcfg5;
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u32 lcdc_lcdcfg6;
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u32 res1;
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u32 lcdc_lcden;
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u32 lcdc_lcddis;
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u32 lcdc_lcdsr;
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u32 res2;
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u32 lcdc_lcdidr;
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u32 res3[3];
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u32 lcdc_basecher;
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u32 res4[3];
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u32 lcdc_baseidr;
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u32 res5[3];
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u32 lcdc_baseaddr;
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u32 lcdc_basectrl;
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u32 lcdc_basenext;
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u32 lcdc_basecfg0;
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u32 lcdc_basecfg1;
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u32 lcdc_basecfg2;
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u32 lcdc_basecfg3;
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u32 lcdc_basecfg4;
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};
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#define LCDC_LCDCFG0_CLKPOL (0x1 << 0)
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#define LCDC_LCDCFG0_CLKSEL (0x1 << 2)
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#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3)
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#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8)
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#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9)
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#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11)
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#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12)
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#define LCDC_LCDCFG0_CLKDIV_Pos 16
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#define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos)
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#define LCDC_LCDCFG0_CLKDIV(value) \
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((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
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#define LCDC_LCDCFG1_HSPW_Pos 0
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#define LCDC_LCDCFG1_HSPW_Msk (0x3f << LCDC_LCDCFG1_HSPW_Pos)
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#define LCDC_LCDCFG1_HSPW(value) \
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((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
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#define LCDC_LCDCFG1_VSPW_Pos 16
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#define LCDC_LCDCFG1_VSPW_Msk (0x3f << LCDC_LCDCFG1_VSPW_Pos)
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#define LCDC_LCDCFG1_VSPW(value) \
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((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
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#define LCDC_LCDCFG2_VFPW_Pos 0
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#define LCDC_LCDCFG2_VFPW_Msk (0x3f << LCDC_LCDCFG2_VFPW_Pos)
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#define LCDC_LCDCFG2_VFPW(value) \
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((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
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#define LCDC_LCDCFG2_VBPW_Pos 16
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#define LCDC_LCDCFG2_VBPW_Msk (0x3f << LCDC_LCDCFG2_VBPW_Pos)
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#define LCDC_LCDCFG2_VBPW(value) \
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((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
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#define LCDC_LCDCFG3_HFPW_Pos 0
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#define LCDC_LCDCFG3_HFPW_Msk (0xff << LCDC_LCDCFG3_HFPW_Pos)
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#define LCDC_LCDCFG3_HFPW(value) \
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((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
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#define LCDC_LCDCFG3_HBPW_Pos 16
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#define LCDC_LCDCFG3_HBPW_Msk (0xff << LCDC_LCDCFG3_HBPW_Pos)
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#define LCDC_LCDCFG3_HBPW(value) \
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((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
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#define LCDC_LCDCFG4_PPL_Pos 0
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#define LCDC_LCDCFG4_PPL_Msk (0x7ff << LCDC_LCDCFG4_PPL_Pos)
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#define LCDC_LCDCFG4_PPL(value) \
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((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
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#define LCDC_LCDCFG4_RPF_Pos 16
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#define LCDC_LCDCFG4_RPF_Msk (0x7ff << LCDC_LCDCFG4_RPF_Pos)
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#define LCDC_LCDCFG4_RPF(value) \
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((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
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#define LCDC_LCDCFG5_HSPOL (0x1 << 0)
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#define LCDC_LCDCFG5_VSPOL (0x1 << 1)
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#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2)
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#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3)
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#define LCDC_LCDCFG5_DISPPOL (0x1 << 4)
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#define LCDC_LCDCFG5_SERIAL (0x1 << 5)
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#define LCDC_LCDCFG5_DITHER (0x1 << 6)
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#define LCDC_LCDCFG5_DISPDLY (0x1 << 7)
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#define LCDC_LCDCFG5_MODE_Pos 8
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#define LCDC_LCDCFG5_MODE_Msk (0x3 << LCDC_LCDCFG5_MODE_Pos)
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#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8)
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#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8)
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#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8)
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#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8)
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#define LCDC_LCDCFG5_VSPSU (0x1 << 12)
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#define LCDC_LCDCFG5_VSPHO (0x1 << 13)
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#define LCDC_LCDCFG5_GUARDTIME_Pos 16
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#define LCDC_LCDCFG5_GUARDTIME_Msk (0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
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#define LCDC_LCDCFG5_GUARDTIME(value) \
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((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
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#define LCDC_LCDCFG6_PWMPS_Pos 0
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#define LCDC_LCDCFG6_PWMPS_Msk (0x7 << LCDC_LCDCFG6_PWMPS_Pos)
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#define LCDC_LCDCFG6_PWMPS(value) \
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((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
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#define LCDC_LCDCFG6_PWMPOL (0x1 << 4)
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#define LCDC_LCDCFG6_PWMCVAL_Pos 8
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#define LCDC_LCDCFG6_PWMCVAL_Msk (0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
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#define LCDC_LCDCFG6_PWMCVAL(value) \
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((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
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#define LCDC_LCDEN_CLKEN (0x1 << 0)
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#define LCDC_LCDEN_SYNCEN (0x1 << 1)
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#define LCDC_LCDEN_DISPEN (0x1 << 2)
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#define LCDC_LCDEN_PWMEN (0x1 << 3)
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#define LCDC_LCDDIS_CLKDIS (0x1 << 0)
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#define LCDC_LCDDIS_SYNCDIS (0x1 << 1)
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#define LCDC_LCDDIS_DISPDIS (0x1 << 2)
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#define LCDC_LCDDIS_PWMDIS (0x1 << 3)
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#define LCDC_LCDDIS_CLKRST (0x1 << 8)
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#define LCDC_LCDDIS_SYNCRST (0x1 << 9)
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#define LCDC_LCDDIS_DISPRST (0x1 << 10)
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#define LCDC_LCDDIS_PWMRST (0x1 << 11)
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#define LCDC_LCDSR_CLKSTS (0x1 << 0)
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#define LCDC_LCDSR_LCDSTS (0x1 << 1)
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#define LCDC_LCDSR_DISPSTS (0x1 << 2)
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#define LCDC_LCDSR_PWMSTS (0x1 << 3)
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#define LCDC_LCDSR_SIPSTS (0x1 << 4)
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#define LCDC_LCDIDR_SOFID (0x1 << 0)
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#define LCDC_LCDIDR_DISID (0x1 << 1)
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#define LCDC_LCDIDR_DISPID (0x1 << 2)
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#define LCDC_LCDIDR_FIFOERRID (0x1 << 4)
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#define LCDC_LCDIDR_BASEID (0x1 << 8)
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#define LCDC_LCDIDR_OVR1ID (0x1 << 9)
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#define LCDC_LCDIDR_HEOID (0x1 << 11)
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#define LCDC_LCDIDR_HCRID (0x1 << 12)
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#define LCDC_BASECHER_CHEN (0x1 << 0)
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#define LCDC_BASECHER_UPDATEEN (0x1 << 1)
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#define LCDC_BASECHER_A2QEN (0x1 << 2)
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#define LCDC_BASEIDR_DMA (0x1 << 2)
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#define LCDC_BASEIDR_DSCR (0x1 << 3)
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#define LCDC_BASEIDR_ADD (0x1 << 4)
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#define LCDC_BASEIDR_DONE (0x1 << 5)
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#define LCDC_BASEIDR_OVR (0x1 << 6)
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#define LCDC_BASECTRL_DFETCH (0x1 << 0)
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#define LCDC_BASECTRL_LFETCH (0x1 << 1)
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#define LCDC_BASECTRL_DMAIEN (0x1 << 2)
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#define LCDC_BASECTRL_DSCRIEN (0x1 << 3)
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#define LCDC_BASECTRL_ADDIEN (0x1 << 4)
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#define LCDC_BASECTRL_DONEIEN (0x1 << 5)
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#define LCDC_BASECFG0_BLEN_Pos 4
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#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4)
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#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4)
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#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4)
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#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4)
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#define LCDC_BASECFG0_DLBO (0x1 << 8)
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#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4)
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#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4)
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#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4)
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#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4)
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#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4)
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#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4)
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#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4)
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#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4)
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#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4)
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#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4)
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#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4)
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#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4)
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#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4)
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#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4)
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#define LCDC_BASECFG2_XSTRIDE_Pos 0
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#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
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#define LCDC_BASECFG2_XSTRIDE(value) \
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((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
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#define LCDC_BASECFG3_BDEF_Pos 0
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#define LCDC_BASECFG3_BDEF_Msk (0xff << LCDC_BASECFG3_BDEF_Pos)
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#define LCDC_BASECFG3_BDEF(value) \
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((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
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#define LCDC_BASECFG3_GDEF_Pos 8
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#define LCDC_BASECFG3_GDEF_Msk (0xff << LCDC_BASECFG3_GDEF_Pos)
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#define LCDC_BASECFG3_GDEF(value) \
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((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
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#define LCDC_BASECFG3_RDEF_Pos 16
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#define LCDC_BASECFG3_RDEF_Msk (0xff << LCDC_BASECFG3_RDEF_Pos)
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#define LCDC_BASECFG3_RDEF(value) \
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((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
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#define LCDC_BASECLUT_BCLUT_Pos 0
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#define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos)
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#define LCDC_BASECLUT_GCLUT_Pos 8
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#define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos)
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#define LCDC_BASECLUT_RCLUT_Pos 16
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#define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos)
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#define LCDC_BASECFG4_DMA (0x1 << 8)
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#define LCDC_BASECFG4_REP (0x1 << 9)
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struct lcd_dma_desc {
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u32 address;
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u32 control;
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u32 next;
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};
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#define ATMEL_LCDC_LUT(n) (0x0400 + ((n)*4))
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#endif /* __ATMEL_HLCDC_H__ */
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