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https://github.com/brain-hackers/u-boot-brain
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41c881c0ca
In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. If these steps aren't followed, GPT timer may stop and the kernel stops at "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> |
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| .. | ||
| am33xx | ||
| highbank | ||
| mx5 | ||
| omap3 | ||
| omap4 | ||
| omap-common | ||
| s5p-common | ||
| s5pc1xx | ||
| s5pc2xx | ||
| tegra2 | ||
| u8500 | ||
| cache_v7.c | ||
| config.mk | ||
| cpu.c | ||
| Makefile | ||
| start.S | ||
| syslib.c | ||
| u-boot.lds | ||