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550650ddd0
This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
45 lines
1.7 KiB
C
45 lines
1.7 KiB
C
/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PPC460SX_H_
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#define _PPC460SX_H_
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
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/* Memory mapped registers */
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#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
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#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
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#define SDR0_SRST0_DMC 0x00200000
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#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
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#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
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#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
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#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
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#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
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#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
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#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
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#endif /* _PPC460SX_H_ */
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