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644362c40a
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for more information. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom boards using: CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <sfalco@harris.com> CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <eibach@gdsys.de> Signed-off-by: Steve Falco <sfalco@harris.com> Acked-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
96 lines
3.5 KiB
C
96 lines
3.5 KiB
C
/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PPC405EX_H_
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#define _PPC405EX_H_
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
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#define CONFIG_NAND_NDFC
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/* Memory mapped register */
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#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
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#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
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/* SDR */
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#define SDR0_SDCS0 0x0060
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#define SDR0_UART0 0x0120 /* UART0 Config */
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#define SDR0_UART1 0x0121 /* UART1 Config */
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#define SDR0_SRST 0x0200
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#define SDR0_CUST0 0x4000
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#define SDR0_PFC0 0x4100
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#define SDR0_PFC1 0x4101
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#define SDR0_MFR 0x4300 /* SDR0_MFR reg */
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#define SDR0_ECID0 0x0080
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#define SDR0_ECID1 0x0081
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#define SDR0_ECID2 0x0082
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#define SDR0_ECID3 0x0083
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#define SDR0_SDCS_SDD (0x80000000 >> 31)
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#define SDR0_SRST_DMC (0x80000000 >> 10)
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#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
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#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
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#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
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#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
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#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
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#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
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#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
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#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
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#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */
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#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */
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#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
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#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24)
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#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF)
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#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
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#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22)
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#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3)
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#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
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#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
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#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
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#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
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#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
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#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
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#define SDR0_PFC1_U1ME 0x02000000
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#define SDR0_PFC1_U0ME 0x00080000
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#define SDR0_PFC1_U0IM 0x00040000
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#define SDR0_PFC1_SIS 0x00020000
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#define SDR0_PFC1_DMAAEN 0x00010000
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#define SDR0_PFC1_DMADEN 0x00008000
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#define SDR0_PFC1_USBEN 0x00004000
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#define SDR0_PFC1_AHBSWAP 0x00000020
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#define SDR0_PFC1_USBBIGEN 0x00000010
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#define SDR0_PFC1_GPT_FREQ 0x0000000f
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#endif /* _PPC405EX_H_ */
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