mirror of
https://github.com/brain-hackers/u-boot-brain
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eb53941206
Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
38 lines
1.1 KiB
C
38 lines
1.1 KiB
C
/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _ASM_MP_H_
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#define _ASM_MP_H_
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#include <lmb.h>
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void setup_mp(void);
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void cpu_mp_lmb_reserve(struct lmb *lmb);
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u32 determine_mp_bootpg(unsigned int *pagesize);
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int is_core_disabled(int nr);
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#ifdef CONFIG_E6500
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#define thread_to_core(x) (x >> 1)
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#else
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#define thread_to_core(x) (x)
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#endif
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#endif
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