mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
![Marcin Niestroj](/assets/img/avatar_default.png)
Import chiliSOM and chiliboard dts files from Linux v4.19. They will be used after transition to driver model and device-tree based boot. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
179 lines
4.5 KiB
Plaintext
179 lines
4.5 KiB
Plaintext
/*
|
|
* Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
|
|
* Author: Rostislav Lisovy <lisovy@jablotron.cz>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#include "am33xx.dtsi"
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
|
|
/ {
|
|
model = "Grinn AM335x ChiliSOM";
|
|
compatible = "grinn,am335x-chilisom", "ti,am33xx";
|
|
|
|
cpus {
|
|
cpu@0 {
|
|
cpu0-supply = <&dcdc2_reg>;
|
|
};
|
|
};
|
|
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x80000000 0x20000000>; /* 512 MB */
|
|
};
|
|
};
|
|
|
|
&am33xx_pinmux {
|
|
pinctrl-names = "default";
|
|
|
|
i2c0_pins: pinmux_i2c0_pins {
|
|
pinctrl-single,pins = <
|
|
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
|
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
|
>;
|
|
};
|
|
|
|
nandflash_pins: nandflash_pins {
|
|
pinctrl-single,pins = <
|
|
AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
|
AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
|
AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
|
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
|
AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
|
AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
|
AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
|
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
|
|
|
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
|
AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
|
AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
|
AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
|
AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
|
AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
|
>;
|
|
};
|
|
};
|
|
|
|
&i2c0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
tps: tps@24 {
|
|
reg = <0x24>;
|
|
};
|
|
|
|
};
|
|
|
|
/include/ "tps65217.dtsi"
|
|
|
|
&tps {
|
|
regulators {
|
|
dcdc1_reg: regulator@0 {
|
|
regulator-name = "vdds_dpr";
|
|
regulator-always-on;
|
|
};
|
|
|
|
dcdc2_reg: regulator@1 {
|
|
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
|
regulator-name = "vdd_mpu";
|
|
regulator-min-microvolt = <925000>;
|
|
regulator-max-microvolt = <1325000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
dcdc3_reg: regulator@2 {
|
|
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
|
regulator-name = "vdd_core";
|
|
regulator-min-microvolt = <925000>;
|
|
regulator-max-microvolt = <1150000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo1_reg: regulator@3 {
|
|
regulator-name = "vio,vrtc,vdds";
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo2_reg: regulator@4 {
|
|
regulator-name = "vdd_3v3aux";
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo3_reg: regulator@5 {
|
|
regulator-name = "vdd_1v8";
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo4_reg: regulator@6 {
|
|
regulator-name = "vdd_3v3d";
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rtc {
|
|
system-power-controller;
|
|
|
|
pinctrl-0 = <&ext_wakeup>;
|
|
pinctrl-names = "default";
|
|
|
|
ext_wakeup: ext-wakeup {
|
|
pins = "ext_wakeup0";
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
/* NAND Flash */
|
|
&elm {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpmc {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&nandflash_pins>;
|
|
ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
|
|
nand@0,0 {
|
|
compatible = "ti,omap2-nand";
|
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
|
interrupt-parent = <&gpmc>;
|
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
|
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
|
ti,nand-ecc-opt = "bch8";
|
|
ti,elm-id = <&elm>;
|
|
nand-bus-width = <8>;
|
|
gpmc,device-width = <1>;
|
|
gpmc,sync-clk-ps = <0>;
|
|
gpmc,cs-on-ns = <0>;
|
|
gpmc,cs-rd-off-ns = <44>;
|
|
gpmc,cs-wr-off-ns = <44>;
|
|
gpmc,adv-on-ns = <6>;
|
|
gpmc,adv-rd-off-ns = <34>;
|
|
gpmc,adv-wr-off-ns = <44>;
|
|
gpmc,we-on-ns = <0>;
|
|
gpmc,we-off-ns = <40>;
|
|
gpmc,oe-on-ns = <0>;
|
|
gpmc,oe-off-ns = <54>;
|
|
gpmc,access-ns = <64>;
|
|
gpmc,rd-cycle-ns = <82>;
|
|
gpmc,wr-cycle-ns = <82>;
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
gpmc,clk-activation-ns = <0>;
|
|
gpmc,wr-access-ns = <40>;
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
};
|
|
};
|