mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 21:33:24 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
350 lines
7.4 KiB
C
350 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/mc_cgm_regs.h>
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#include <asm/arch/mc_me_regs.h>
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#include <asm/arch/mc_rgm_regs.h>
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#include <netdev.h>
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#include <div64.h>
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#include <errno.h>
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u32 get_cpu_rev(void)
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{
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struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
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u32 cpu = readl(&mscmir->cpxtype);
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return cpu;
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}
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DECLARE_GLOBAL_DATA_PTR;
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static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
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u32 pllfd, u32 selected_output)
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{
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u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
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u32 plldv_rfdphi_div = 0, fout = 0;
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u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
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if (selected_output > DFS_MAXNUMBER) {
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return -1;
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}
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plldv_prediv =
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(plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
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plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
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pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
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plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
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/* The formula for VCO is from TR manual, rev. D */
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vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
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if (selected_output != 0) {
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/* Determine the RFDPHI for PHI1 */
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plldv_rfdphi_div =
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(plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
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PLLDIG_PLLDV_RFDPHI1_OFFSET;
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plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
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if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
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dfs_portn =
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readl(DFS_DVPORTn(pll, selected_output - 1));
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dfs_mfi =
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(dfs_portn & DFS_DVPORTn_MFI_MASK) >>
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DFS_DVPORTn_MFI_OFFSET;
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dfs_mfn =
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(dfs_portn & DFS_DVPORTn_MFI_MASK) >>
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DFS_DVPORTn_MFI_OFFSET;
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fout = vco / (dfs_mfi + (dfs_mfn / 256));
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} else {
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fout = vco / plldv_rfdphi_div;
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}
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} else {
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/* Determine the RFDPHI for PHI0 */
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plldv_rfdphi_div =
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(plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
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PLLDIG_PLLDV_RFDPHI_OFFSET;
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fout = vco / plldv_rfdphi_div;
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}
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return fout;
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}
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/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
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static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
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u32 selected_output)
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{
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u32 plldv, pllfd;
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plldv = readl(PLLDIG_PLLDV(pll));
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pllfd = readl(PLLDIG_PLLFD(pll));
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return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
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}
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static u32 get_mcu_main_clk(void)
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{
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u32 coreclk_div;
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u32 sysclk_sel;
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u32 freq = 0;
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sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
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sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
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coreclk_div =
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readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
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coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
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coreclk_div += 1;
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switch (sysclk_sel) {
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case MC_CGM_SC_SEL_FIRC:
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freq = FIRC_CLK_FREQ;
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break;
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case MC_CGM_SC_SEL_XOSC:
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freq = XOSC_CLK_FREQ;
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break;
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case MC_CGM_SC_SEL_ARMPLL:
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/* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
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freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
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break;
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case MC_CGM_SC_SEL_CLKDISABLE:
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printf("Sysclk is disabled\n");
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break;
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default:
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printf("unsupported system clock select\n");
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}
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return freq / coreclk_div;
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}
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static u32 get_sys_clk(u32 number)
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{
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u32 sysclk_div, sysclk_div_number;
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u32 sysclk_sel;
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u32 freq = 0;
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switch (number) {
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case 3:
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sysclk_div_number = 0;
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break;
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case 6:
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sysclk_div_number = 1;
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break;
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default:
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printf("unsupported system clock \n");
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return -1;
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}
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sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
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sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
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sysclk_div =
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readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
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MC_CGM_SC_DCn_PREDIV_MASK;
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sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
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sysclk_div += 1;
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switch (sysclk_sel) {
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case MC_CGM_SC_SEL_FIRC:
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freq = FIRC_CLK_FREQ;
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break;
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case MC_CGM_SC_SEL_XOSC:
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freq = XOSC_CLK_FREQ;
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break;
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case MC_CGM_SC_SEL_ARMPLL:
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/* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
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freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
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break;
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case MC_CGM_SC_SEL_CLKDISABLE:
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printf("Sysclk is disabled\n");
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break;
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default:
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printf("unsupported system clock select\n");
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}
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return freq / sysclk_div;
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}
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static u32 get_peripherals_clk(void)
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{
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u32 aux5clk_div;
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u32 freq = 0;
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aux5clk_div =
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readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
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MC_CGM_ACn_DCm_PREDIV_MASK;
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aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
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aux5clk_div += 1;
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freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
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return freq / aux5clk_div;
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}
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static u32 get_uart_clk(void)
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{
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u32 auxclk3_div, auxclk3_sel, freq = 0;
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auxclk3_sel =
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readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
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auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
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auxclk3_div =
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readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
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MC_CGM_ACn_DCm_PREDIV_MASK;
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auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
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auxclk3_div += 1;
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switch (auxclk3_sel) {
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case MC_CGM_ACn_SEL_FIRC:
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freq = FIRC_CLK_FREQ;
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break;
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case MC_CGM_ACn_SEL_XOSC:
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freq = XOSC_CLK_FREQ;
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break;
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case MC_CGM_ACn_SEL_PERPLLDIVX:
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freq = get_peripherals_clk() / 3;
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break;
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case MC_CGM_ACn_SEL_SYSCLK:
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freq = get_sys_clk(6);
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break;
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default:
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printf("unsupported system clock select\n");
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}
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return freq / auxclk3_div;
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}
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static u32 get_fec_clk(void)
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{
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u32 aux2clk_div;
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u32 freq = 0;
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aux2clk_div =
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readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
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MC_CGM_ACn_DCm_PREDIV_MASK;
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aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
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aux2clk_div += 1;
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freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
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return freq / aux2clk_div;
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}
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static u32 get_usdhc_clk(void)
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{
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u32 aux15clk_div;
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u32 freq = 0;
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aux15clk_div =
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readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
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MC_CGM_ACn_DCm_PREDIV_MASK;
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aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
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aux15clk_div += 1;
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freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
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return freq / aux15clk_div;
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}
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static u32 get_i2c_clk(void)
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{
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return get_peripherals_clk();
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}
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/* return clocks in Hz */
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return get_mcu_main_clk();
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case MXC_PERIPHERALS_CLK:
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return get_peripherals_clk();
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case MXC_UART_CLK:
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return get_uart_clk();
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case MXC_FEC_CLK:
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return get_fec_clk();
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case MXC_I2C_CLK:
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return get_i2c_clk();
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case MXC_USDHC_CLK:
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return get_usdhc_clk();
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default:
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break;
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}
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printf("Error: Unsupported function to read the frequency! \
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Please define it correctly!");
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return -1;
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}
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/* Not yet implemented - int soc_clk_dump(); */
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#if defined(CONFIG_DISPLAY_CPUINFO)
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static char *get_reset_cause(void)
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{
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u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
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switch (cause) {
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case F_SWT4:
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return "WDOG";
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case F_JTAG:
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return "JTAG";
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case F_FCCU_SOFT:
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return "FCCU soft reaction";
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case F_FCCU_HARD:
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return "FCCU hard reaction";
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case F_SOFT_FUNC:
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return "Software Functional reset";
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case F_ST_DONE:
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return "Self Test done reset";
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case F_EXT_RST:
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return "External reset";
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default:
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return "unknown reset";
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}
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}
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#define SRC_SCR_SW_RST (1<<12)
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void reset_cpu(ulong addr)
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{
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printf("Feature not supported.\n");
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};
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int print_cpuinfo(void)
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{
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printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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printf("Reset cause: %s\n", get_reset_cause());
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return 0;
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}
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#endif
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int cpu_eth_init(bd_t * bis)
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{
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int rc = -ENODEV;
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#if defined(CONFIG_FEC_MXC)
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rc = fecmxc_initialize(bis);
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#endif
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return rc;
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}
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int get_clocks(void)
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{
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#ifdef CONFIG_FSL_ESDHC
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gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
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#endif
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return 0;
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}
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