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https://github.com/brain-hackers/u-boot-brain
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74749f1e84
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
29 lines
1.0 KiB
Makefile
29 lines
1.0 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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obj-y += pinctrl-uclass.o
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obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
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obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
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obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
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obj-y += nxp/
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obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += rockchip/
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obj-$(CONFIG_ARCH_ASPEED) += aspeed/
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obj-$(CONFIG_ARCH_ATH79) += ath79/
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obj-$(CONFIG_PINCTRL_INTEL) += intel/
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obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
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obj-$(CONFIG_ARCH_RMOBILE) += renesas/
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obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
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obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
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obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o
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obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
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obj-$(CONFIG_PINCTRL_MESON) += meson/
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obj-$(CONFIG_PINCTRL_MTK) += mediatek/
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obj-$(CONFIG_PINCTRL_MSCC) += mscc/
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obj-$(CONFIG_ARCH_MVEBU) += mvebu/
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obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
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obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
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obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
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obj-$(CONFIG_$(SPL_)PINCTRL_STMFX) += pinctrl-stmfx.o
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obj-y += broadcom/
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