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![]() AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> |
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.. | ||
boot.c | ||
bootm.c | ||
cache.c | ||
crt0_riscv_efi.S | ||
elf_riscv32_efi.lds | ||
elf_riscv64_efi.lds | ||
interrupts.c | ||
Makefile | ||
reloc_riscv_efi.c | ||
reset.c | ||
setjmp.S |