Rick Chen 52923c6db7 riscv: cache: Implement i/dcache [status, enable, disable] ... AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>		2018-11-26 13:58:01 +08:00
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boot.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
bootm.c	riscv: align bootm implementation with that of other architectures	2018-11-26 13:57:32 +08:00
cache.c	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
crt0_riscv_efi.S	SPDX: Convert single license tags to Linux Kernel style	2018-05-29 14:44:21 +08:00
elf_riscv32_efi.lds	SPDX: Convert single license tags to Linux Kernel style	2018-05-29 14:44:21 +08:00
elf_riscv64_efi.lds	SPDX: Convert single license tags to Linux Kernel style	2018-05-29 14:44:21 +08:00
interrupts.c	riscv: hang on unhandled exceptions	2018-11-26 13:57:30 +08:00
Makefile	riscv: Move do_reset() to a common place	2018-10-03 17:48:43 +08:00
reloc_riscv_efi.c	riscv: Remove unused _relocate arguments	2018-07-19 16:31:37 -04:00
reset.c	riscv: cosmetic: Reword do_reset() printf message.	2018-10-03 17:49:27 +08:00
setjmp.S	riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I	2018-11-26 13:57:29 +08:00