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![Jagan Teki](/assets/img/avatar_default.png)
Add NAND support for Engicam GEAM6UL board. Boot Log: -------- U-Boot SPL 2016.11-g537fa5f (Nov 28 2016 - 11:42:28) Trying to boot from NAND NAND : 256 MiB U-Boot 2016.11-g537fa5f (Nov 28 2016 - 11:20:06 +0100) CPU: Freescale i.MX6UL rev1.1 69 MHz (running at 396 MHz) CPU: Automotive temperature grade (-40C to 125C) at 42C Reset cause: WDOG Model: Engicam GEAM6UL DRAM: 128 MiB NAND: 256 MiB MMC: FSL_SDHC: 0 * Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
318 lines
8.4 KiB
C
318 lines
8.4 KiB
C
/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/iomux-v3.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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return 0;
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}
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#ifdef CONFIG_NAND_MXS
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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static iomux_v3_cfg_t const nand_pads[] = {
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MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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};
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
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clrbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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/*
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* config gpmi and bch clock to 100 MHz
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* bch/gpmi select PLL2 PFD2 400M
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* 100M = 400M / 4
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*/
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clrbits_le32(&mxc_ccm->cscmr1,
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MXC_CCM_CSCMR1_BCH_CLK_SEL |
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MXC_CCM_CSCMR1_GPMI_CLK_SEL);
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clrsetbits_le32(&mxc_ccm->cscdr1,
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MXC_CCM_CSCDR1_BCH_PODF_MASK |
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MXC_CCM_CSCDR1_GPMI_PODF_MASK,
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(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
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(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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#endif /* CONFIG_NAND_MXS */
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <libfdt.h>
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#include <spl.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-ddr.h>
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/* MMC board initialization is needed till adding DM support in SPL */
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#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* VSELECT */
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MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* CD */
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MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* RST_B */
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MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
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struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC1_BASE_ADDR, 0, 4},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-boot device node) (Physical Port)
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* mmc0 USDHC1
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(
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usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
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gpio_direction_input(USDHC1_CD_GPIO);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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default:
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printf("Warning - USDHC%d controller not supporting\n",
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i + 1);
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return 0;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret) {
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printf("Warning: failed to initialize mmc dev %d\n", i);
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return ret;
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}
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}
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return 0;
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}
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#endif /* CONFIG_FSL_ESDHC */
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000030,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ddr_type = 0x000c0000,
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};
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_odt0 = 0x00000030,
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.dram_odt1 = 0x00000030,
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.dram_sdba2 = 0x00000000,
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.dram_sdclk_0 = 0x00000008,
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.dram_sdqs0 = 0x00000038,
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.dram_sdqs1 = 0x00000030,
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.dram_reset = 0x00000030,
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};
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static struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00070007,
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.p0_mpdgctrl0 = 0x41490145,
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.p0_mprddlctl = 0x40404546,
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.p0_mpwrdlctl = 0x4040524D,
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};
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struct mx6_ddr_sysinfo ddr_sysinfo = {
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.dsize = 0,
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.cs_density = 20,
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 2,
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.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.ddr_type = DDR_TYPE_DDR3,
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 800,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 13,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0xFFFFFFFF, &ccm->CCGR0);
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writel(0xFFFFFFFF, &ccm->CCGR1);
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writel(0xFFFFFFFF, &ccm->CCGR2);
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writel(0xFFFFFFFF, &ccm->CCGR3);
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writel(0xFFFFFFFF, &ccm->CCGR4);
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writel(0xFFFFFFFF, &ccm->CCGR5);
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writel(0xFFFFFFFF, &ccm->CCGR6);
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writel(0xFFFFFFFF, &ccm->CCGR7);
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}
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static void spl_dram_init(void)
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{
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mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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void board_init_f(ulong dummy)
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{
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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ccgr_init();
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/* iomux and setup of i2c */
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board_early_init_f();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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#endif /* CONFIG_SPL_BUILD */
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