mirror of
https://github.com/brain-hackers/u-boot-brain
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de9ac9a1b9
This adds initial Intel Braswell SoC support. It uses Intel FSP to initialize the chipset. Similar to its predecessor BayTrail, there are some work to do to enable the legacy UART integrated in the Braswell SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
51 lines
1.0 KiB
C
51 lines
1.0 KiB
C
/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _BRASWELL_IOMAP_H_
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#define _BRASWELL_IOMAP_H_
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/* Memory Mapped IO bases */
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/* Power Management Controller */
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#define PMC_BASE_ADDRESS 0xfed03000
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#define PMC_BASE_SIZE 0x400
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/* Power Management Unit */
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#define PUNIT_BASE_ADDRESS 0xfed05000
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#define PUNIT_BASE_SIZE 0x800
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/* Intel Legacy Block */
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#define ILB_BASE_ADDRESS 0xfed08000
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#define ILB_BASE_SIZE 0x400
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/* SPI Bus */
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#define SPI_BASE_ADDRESS 0xfed01000
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#define SPI_BASE_SIZE 0x400
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/* Root Complex Base Address */
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#define RCBA_BASE_ADDRESS 0xfed1c000
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#define RCBA_BASE_SIZE 0x400
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/* IO Memory */
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#define IO_BASE_ADDRESS 0xfed80000
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#define IO_BASE_SIZE 0x4000
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/* MODPHY */
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#define MPHY_BASE_ADDRESS 0xfef00000
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#define MPHY_BASE_SIZE 0x100000
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/* IO Port bases */
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#define ACPI_BASE_ADDRESS 0x400
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#define ACPI_BASE_SIZE 0x80
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#define GPIO_BASE_ADDRESS 0x500
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#define GPIO_BASE_SIZE 0x100
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#define SMBUS_BASE_ADDRESS 0xefa0
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#endif /* _BRASWELL_IOMAP_H_ */
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