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![Eric Nelson](/assets/img/avatar_default.png)
Update DDR calibration settings based on a larger test set. The initial values were gathered on a small number of boards, and have been found to fail on some boards under load. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
43 lines
1.5 KiB
INI
43 lines
1.5 KiB
INI
/*
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* Copyright (C) 2013 Boundary Devices
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
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DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
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DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
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DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
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DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
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DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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