mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-26 22:50:33 +09:00
32afad783e
Both big-endian and little-endian are tested with below commands: Rom version: (Default, Now we config it as rom version) qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic Ram version: qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
88 lines
2.1 KiB
C
88 lines
2.1 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mipsregs.h>
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static unsigned long timestamp;
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/* how many counter cycles in a jiffy */
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#define CYCLES_PER_JIFFY \
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(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
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/*
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* timer without interrupts
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*/
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int timer_init(void)
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{
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/* Set up the timer for the first expiration. */
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timestamp = 0;
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write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
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return 0;
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}
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ulong get_timer(ulong base)
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{
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unsigned int count;
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unsigned int expirelo = read_c0_compare();
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/* Check to see if we have missed any timestamps. */
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count = read_c0_count();
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while ((count - expirelo) < 0x7fffffff) {
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expirelo += CYCLES_PER_JIFFY;
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timestamp++;
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}
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write_c0_compare(expirelo);
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return timestamp - base;
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}
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void __udelay(unsigned long usec)
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{
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unsigned int tmo;
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tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
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while ((tmo - read_c0_count()) < 0x7fffffff)
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/*NOP*/;
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On MIPS it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On MIPS it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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