mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-25 04:19:43 +09:00
412ae53aad
Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB or 128MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
46 lines
1000 B
ArmAsm
46 lines
1000 B
ArmAsm
/*
|
|
* WORK Microwave work_92105 board low level init
|
|
*
|
|
* (C) Copyright 2014 DENX Software Engineering GmbH
|
|
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
|
|
*
|
|
* Low level init is called from SPL to set up the clocks.
|
|
* On entry, the LPC3250 is in Direct Run mode with all clocks
|
|
* running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is
|
|
* 104 MHz and PCLK is 13 MHz.
|
|
*
|
|
* This code must run from SRAM so that the clock changes do
|
|
* not prevent it from executing.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
.globl lowlevel_init
|
|
|
|
lowlevel_init:
|
|
|
|
/* Set ARM, HCLK, PCLK dividers for normal mode */
|
|
ldr r0, =0x0000003D
|
|
ldr r1, =0x40004040
|
|
str r0, [r1]
|
|
|
|
/* Start HCLK PLL for 208 MHz */
|
|
ldr r0, =0x0001401E
|
|
ldr r1, =0x40004058
|
|
str r0, [r1]
|
|
|
|
/* wait for HCLK PLL to lock */
|
|
1:
|
|
ldr r0, [r1]
|
|
ands r0, r0, #1
|
|
beq 1b
|
|
|
|
/* switch to normal mode */
|
|
ldr r1, =0x40004044
|
|
ldr r0, [r1]
|
|
orr r0, #0x00000004
|
|
str r0, [r1]
|
|
|
|
/* Return to U-boot via saved link register */
|
|
mov pc, lr
|