mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-25 03:18:51 +09:00
![Stefano Babic](/assets/img/avatar_default.png)
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
467 lines
10 KiB
C
467 lines
10 KiB
C
/*
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* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/spi.h>
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#ifdef CONFIG_MX27
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/* i.MX27 has a completely wrong register layout and register definitions in the
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* datasheet, the correct one is in the Freescale's Linux driver */
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#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
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"See linux mxc_spi driver from Freescale for details."
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#endif
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static unsigned long spi_bases[] = {
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MXC_SPI_BASE_ADDRESSES
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};
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__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return -1;
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}
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#define OUT MXC_GPIO_DIRECTION_OUT
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#define reg_read readl
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#define reg_write(a, v) writel(v, a)
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#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
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#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
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#endif
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struct mxc_spi_slave {
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struct spi_slave slave;
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unsigned long base;
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u32 ctrl_reg;
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#if defined(MXC_ECSPI)
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u32 cfg_reg;
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#endif
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int gpio;
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int ss_pol;
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unsigned int max_hz;
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unsigned int mode;
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};
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static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct mxc_spi_slave, slave);
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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if (mxcs->gpio > 0)
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gpio_set_value(mxcs->gpio, mxcs->ss_pol);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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if (mxcs->gpio > 0)
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gpio_set_value(mxcs->gpio,
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!(mxcs->ss_pol));
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}
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u32 get_cspi_div(u32 div)
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{
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int i;
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for (i = 0; i < 8; i++) {
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if (div <= (4 << i))
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return i;
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}
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return i;
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}
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#ifdef MXC_CSPI
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static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
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{
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unsigned int ctrl_reg;
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u32 clk_src;
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u32 div;
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unsigned int max_hz = mxcs->max_hz;
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unsigned int mode = mxcs->mode;
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clk_src = mxc_get_clock(MXC_CSPI_CLK);
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div = DIV_ROUND_UP(clk_src, max_hz);
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div = get_cspi_div(div);
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debug("clk %d Hz, div %d, real clk %d Hz\n",
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max_hz, div, clk_src / (4 << div));
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ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
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MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
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MXC_CSPICTRL_DATARATE(div) |
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MXC_CSPICTRL_EN |
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#ifdef CONFIG_MX35
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MXC_CSPICTRL_SSCTL |
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#endif
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MXC_CSPICTRL_MODE;
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if (mode & SPI_CPHA)
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ctrl_reg |= MXC_CSPICTRL_PHA;
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if (mode & SPI_CPOL)
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ctrl_reg |= MXC_CSPICTRL_POL;
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if (mode & SPI_CS_HIGH)
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ctrl_reg |= MXC_CSPICTRL_SSPOL;
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mxcs->ctrl_reg = ctrl_reg;
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return 0;
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}
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#endif
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#ifdef MXC_ECSPI
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static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
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{
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u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
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s32 reg_ctrl, reg_config;
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u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
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u32 pre_div = 0, post_div = 0;
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
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unsigned int max_hz = mxcs->max_hz;
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unsigned int mode = mxcs->mode;
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/*
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* Reset SPI and set all CSs to master mode, if toggling
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* between slave and master mode we might see a glitch
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* on the clock line
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*/
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reg_ctrl = MXC_CSPICTRL_MODE_MASK;
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reg_write(®s->ctrl, reg_ctrl);
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reg_ctrl |= MXC_CSPICTRL_EN;
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reg_write(®s->ctrl, reg_ctrl);
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if (clk_src > max_hz) {
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pre_div = (clk_src - 1) / max_hz;
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/* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
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post_div = fls(pre_div);
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if (post_div > 4) {
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post_div -= 4;
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if (post_div >= 16) {
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printf("Error: no divider for the freq: %d\n",
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max_hz);
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return -1;
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}
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pre_div >>= post_div;
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} else {
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post_div = 0;
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}
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}
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debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
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MXC_CSPICTRL_SELCHAN(cs);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
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MXC_CSPICTRL_PREDIV(pre_div);
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
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MXC_CSPICTRL_POSTDIV(post_div);
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if (mode & SPI_CS_HIGH)
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ss_pol = 1;
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if (mode & SPI_CPOL) {
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sclkpol = 1;
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sclkctl = 1;
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}
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if (mode & SPI_CPHA)
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sclkpha = 1;
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reg_config = reg_read(®s->cfg);
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/*
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* Configuration register setup
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* The MX51 supports different setup for each SS
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*/
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
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(ss_pol << (cs + MXC_CSPICON_SSPOL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
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(sclkpol << (cs + MXC_CSPICON_POL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
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(sclkctl << (cs + MXC_CSPICON_CTL));
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reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
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(sclkpha << (cs + MXC_CSPICON_PHA));
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debug("reg_ctrl = 0x%x\n", reg_ctrl);
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reg_write(®s->ctrl, reg_ctrl);
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debug("reg_config = 0x%x\n", reg_config);
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reg_write(®s->cfg, reg_config);
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/* save config register and control register */
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mxcs->ctrl_reg = reg_ctrl;
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mxcs->cfg_reg = reg_config;
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/* clear interrupt reg */
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reg_write(®s->intr, 0);
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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return 0;
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}
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#endif
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int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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const u8 *dout, u8 *din, unsigned long flags)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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int nbytes = DIV_ROUND_UP(bitlen, 8);
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u32 data, cnt, i;
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
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u32 ts;
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int status;
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debug("%s: bitlen %d dout 0x%x din 0x%x\n",
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__func__, bitlen, (u32)dout, (u32)din);
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mxcs->ctrl_reg = (mxcs->ctrl_reg &
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~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
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MXC_CSPICTRL_BITCOUNT(bitlen - 1);
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reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
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#ifdef MXC_ECSPI
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reg_write(®s->cfg, mxcs->cfg_reg);
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#endif
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/* Clear interrupt register */
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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/*
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* The SPI controller works only with words,
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* check if less than a word is sent.
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* Access to the FIFO is only 32 bit
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*/
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if (bitlen % 32) {
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data = 0;
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cnt = (bitlen % 32) / 8;
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if (dout) {
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for (i = 0; i < cnt; i++) {
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data = (data << 8) | (*dout++ & 0xFF);
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}
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}
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debug("Sending SPI 0x%x\n", data);
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reg_write(®s->txdata, data);
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nbytes -= cnt;
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}
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data = 0;
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while (nbytes > 0) {
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data = 0;
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if (dout) {
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/* Buffer is not 32-bit aligned */
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if ((unsigned long)dout & 0x03) {
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data = 0;
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for (i = 0; i < 4; i++)
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data = (data << 8) | (*dout++ & 0xFF);
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} else {
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data = *(u32 *)dout;
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data = cpu_to_be32(data);
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dout += 4;
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}
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}
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debug("Sending SPI 0x%x\n", data);
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reg_write(®s->txdata, data);
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nbytes -= 4;
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}
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/* FIFO is written, now starts the transfer setting the XCH bit */
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reg_write(®s->ctrl, mxcs->ctrl_reg |
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MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
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ts = get_timer(0);
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status = reg_read(®s->stat);
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/* Wait until the TC (Transfer completed) bit is set */
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while ((status & MXC_CSPICTRL_TC) == 0) {
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if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
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printf("spi_xchg_single: Timeout!\n");
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return -1;
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}
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status = reg_read(®s->stat);
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}
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/* Transfer completed, clear any pending request */
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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nbytes = DIV_ROUND_UP(bitlen, 8);
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cnt = nbytes % 32;
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if (bitlen % 32) {
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data = reg_read(®s->rxdata);
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cnt = (bitlen % 32) / 8;
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data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
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debug("SPI Rx unaligned: 0x%x\n", data);
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if (din) {
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memcpy(din, &data, cnt);
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din += cnt;
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}
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nbytes -= cnt;
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}
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while (nbytes > 0) {
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u32 tmp;
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tmp = reg_read(®s->rxdata);
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data = cpu_to_be32(tmp);
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debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
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cnt = min_t(u32, nbytes, sizeof(data));
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if (din) {
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memcpy(din, &data, cnt);
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din += cnt;
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}
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nbytes -= cnt;
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}
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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int n_bytes = DIV_ROUND_UP(bitlen, 8);
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int n_bits;
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int ret;
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u32 blk_size;
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u8 *p_outbuf = (u8 *)dout;
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u8 *p_inbuf = (u8 *)din;
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if (!slave)
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return -1;
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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while (n_bytes > 0) {
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if (n_bytes < MAX_SPI_BYTES)
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blk_size = n_bytes;
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else
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blk_size = MAX_SPI_BYTES;
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n_bits = blk_size * 8;
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ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
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if (ret)
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return ret;
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if (dout)
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p_outbuf += blk_size;
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if (din)
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p_inbuf += blk_size;
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n_bytes -= blk_size;
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}
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if (flags & SPI_XFER_END) {
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spi_cs_deactivate(slave);
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}
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return 0;
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}
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void spi_init(void)
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{
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}
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/*
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* Some SPI devices require active chip-select over multiple
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* transactions, we achieve this using a GPIO. Still, the SPI
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* controller has to be configured to use one of its own chipselects.
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* To use this feature you have to implement board_spi_cs_gpio() to assign
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* a gpio value for each cs (-1 if cs doesn't need to use gpio).
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* You must use some unused on this SPI controller cs between 0 and 3.
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*/
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static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
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unsigned int bus, unsigned int cs)
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{
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int ret;
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mxcs->gpio = board_spi_cs_gpio(bus, cs);
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if (mxcs->gpio == -1)
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return 0;
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ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
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if (ret) {
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printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
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return -EINVAL;
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}
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return 0;
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct mxc_spi_slave *mxcs;
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int ret;
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if (bus >= ARRAY_SIZE(spi_bases))
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return NULL;
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if (max_hz == 0) {
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printf("Error: desired clock is 0\n");
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return NULL;
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}
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mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
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if (!mxcs) {
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puts("mxc_spi: SPI Slave not allocated !\n");
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return NULL;
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}
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mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
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ret = setup_cs_gpio(mxcs, bus, cs);
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if (ret < 0) {
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free(mxcs);
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return NULL;
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}
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mxcs->base = spi_bases[bus];
|
|
mxcs->max_hz = max_hz;
|
|
mxcs->mode = mode;
|
|
|
|
return &mxcs->slave;
|
|
}
|
|
|
|
void spi_free_slave(struct spi_slave *slave)
|
|
{
|
|
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
|
|
|
|
free(mxcs);
|
|
}
|
|
|
|
int spi_claim_bus(struct spi_slave *slave)
|
|
{
|
|
int ret;
|
|
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
|
|
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
|
|
|
|
reg_write(®s->rxdata, 1);
|
|
udelay(1);
|
|
ret = spi_cfg_mxc(mxcs, slave->cs);
|
|
if (ret) {
|
|
printf("mxc_spi: cannot setup SPI controller\n");
|
|
return ret;
|
|
}
|
|
reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
|
|
reg_write(®s->intr, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void spi_release_bus(struct spi_slave *slave)
|
|
{
|
|
/* TODO: Shut the controller down */
|
|
}
|