Roy Zang 9458f6d83a T4/serdes: fix the serdes clock frequency ... Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>		2013-05-14 16:00:25 -05:00
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ddr.c	powerpc/t4qds: Add T4QDS board	2012-10-22 15:52:46 -05:00
eth.c	powerpc/t4qds: Add T4QDS board	2012-10-22 15:52:46 -05:00
law.c	board/T4240qds:Fix TLB and LAW size of NAND flash	2013-01-30 11:25:09 -06:00
Makefile	powerpc/t4qds: Add T4QDS board	2012-10-22 15:52:46 -05:00
pci.c	powerpc/t4qds: Add T4QDS board	2012-10-22 15:52:46 -05:00
t4qds.c	T4/serdes: fix the serdes clock frequency	2013-05-14 16:00:25 -05:00
t4qds.h	powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.c	2013-01-30 11:25:08 -06:00
t4240qds_qixis.h	powerpc/t4qds: Add T4QDS board	2012-10-22 15:52:46 -05:00
tlb.c	board/T4240qds:Fix TLB and LAW size of NAND flash	2013-01-30 11:25:09 -06:00