York Sun 316f0d0f8f powerpc: mpc85xx: Fix static TLB table for SDRAM ... Most predefined TLB tables don't have memory coherence bit set for SDRAM. This wasn't an issue before invalidate_dcache_range() function was enabled. Without the coherence bit, dcache invalidation doesn't automatically flush the cache. The coherence bit is already set when dynamic TLB table is used. For some boards with different SPL boot method, or with legacy fixed setting, this bit needs to be set in TLB files. Signed-off-by: York Sun <york.sun@nxp.com>		2017-12-06 14:54:12 -08:00
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ddr.c	Driver/DDR: Moving Freescale DDR driver to a common driver	2013-11-25 11:43:43 -08:00
Kconfig	kconfig: remove redundant "string" type in arch and board Kconfigs	2014-09-13 16:43:55 -04:00
law.c	powerpc/mpc85xx: Cleanup license header in source files	2013-08-12 15:04:24 -07:00
MAINTAINERS	powerpc: fsl: Update maintainers	2017-06-12 12:18:37 -07:00
Makefile	board: powerpc: convert makefiles to Kbuild style	2013-11-01 11:42:12 -04:00
p1_twr.c	env: Rename some other getenv()-related functions	2017-08-16 08:31:11 -04:00
tlb.c	powerpc: mpc85xx: Fix static TLB table for SDRAM	2017-12-06 14:54:12 -08:00