Andy Fleming 3e4c3137d6 e6500: Move L1 enablement after L2 enablement ... The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: Andy Fleming <afleming@freescale.com>		2013-05-14 16:00:25 -05:00
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cpu	e6500: Move L1 enablement after L2 enablement	2013-05-14 16:00:25 -05:00
include/asm	powerpc/mpc85xx: Update corenet global utility block registers	2013-05-14 16:00:24 -05:00
lib	lib: consolidate hang()	2013-05-01 16:41:08 -04:00
config.mk	ppc: Enable generic board support	2013-03-15 16:14:00 -04:00