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https://github.com/brain-hackers/u-boot-brain
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93e6253d11
Early clock initialization is currently done in two stages for OMAP4/5 SoCs. The first stage is the initialization of console clocks and then we initialize basic clocks for functionality necessary for SoC initialization and basic board functionality. By splitting up prcm_init and centralizing this clock initialization, we setup the code for follow on patches that can do board specific initialization such as board detection which will depend on these basic clocks. As part of this change, since the early clock initialization is centralized, we no longer need to expose the console clock initialization. NOTE: we change the sequence slightly by initializing console clocks timer after the io settings are complete, but this is not expected to have any functioanlity impact since we setup the basic IO drive strength initialization as part of do_io_settings. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
87 lines
2.0 KiB
C
87 lines
2.0 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/arch/omap.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/omap_common.h>
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#include <linux/mtd/omap_gpmc.h>
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#include <asm/arch/clock.h>
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#include <asm/ti-common/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Structure for Iodelay configuration registers.
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* Theoretical max for g_delay is 21560 ps.
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* Theoretical max for a_delay is 1/3rd of g_delay max.
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* So using u16 for both a/g_delay.
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*/
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struct iodelay_cfg_entry {
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u16 offset;
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u16 a_delay;
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u16 g_delay;
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};
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struct pad_conf_entry {
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u32 offset;
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u32 val;
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};
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struct omap_sysinfo {
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char *board_string;
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};
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extern const struct omap_sysinfo sysinfo;
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void gpmc_init(void);
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void watchdog_init(void);
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u32 get_device_type(void);
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void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
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void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size);
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void set_muxconf_regs_essential(void);
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u32 wait_on_value(u32, u32, void *, u32);
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void sdelay(unsigned long);
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void setup_early_clocks(void);
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void prcm_init(void);
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void bypass_dpll(u32 const base);
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void freq_update_core(void);
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u32 get_sys_clk_freq(void);
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u32 omap5_ddr_clk(void);
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void cancel_out(u32 *num, u32 *den, u32 den_limit);
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void sdram_init(void);
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u32 omap_sdram_size(void);
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u32 cortex_rev(void);
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void save_omap_boot_params(void);
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void init_omap_revision(void);
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void do_io_settings(void);
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void sri2c_init(void);
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void gpi2c_init(void);
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int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
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u32 warm_reset(void);
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void force_emif_self_refresh(void);
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void get_ioregs(const struct ctrl_ioregs **regs);
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void srcomp_enable(void);
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void setup_warmreset_time(void);
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static inline u32 div_round_up(u32 num, u32 den)
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{
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return (num + den - 1)/den;
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}
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static inline u32 usec_to_32k(u32 usec)
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{
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return div_round_up(32768 * usec, 1000000);
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}
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#define OMAP5_SERVICE_L2ACTLR_SET 0x104
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#define OMAP5_SERVICE_ACR_SET 0x107
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#endif
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