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![Simon Glass](/assets/img/avatar_default.png)
Add a description of how this module works and also some missing function comments. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
911 lines
23 KiB
C
911 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Google, Inc
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*
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* Based on code from the coreboot file of the same name
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <qfw.h>
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#include <asm/atomic.h>
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#include <asm/cpu.h>
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#include <asm/interrupt.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/microcode.h>
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#include <asm/mp.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/processor.h>
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#include <asm/sipi.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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#include <dm/lists.h>
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#include <dm/root.h>
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#include <linux/delay.h>
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#include <linux/linkage.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Setting up multiprocessing
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*
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* See https://www.intel.com/content/www/us/en/intelligent-systems/intel-boot-loader-development-kit/minimal-intel-architecture-boot-loader-paper.html
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*
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* Note that this file refers to the boot CPU (the one U-Boot is running on) as
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* the BSP (BootStrap Processor) and the others as APs (Application Processors).
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*
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* This module works by loading some setup code into RAM at AP_DEFAULT_BASE and
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* telling each AP to execute it. The code that each AP runs is in
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* sipi_vector.S (see ap_start16) which includes a struct sipi_params at the
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* end of it. Those parameters are set up by the C code.
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* Setting up is handled by load_sipi_vector(). It inits the common block of
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* parameters (sipi_params) which tell the APs what to do. This block includes
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* microcode and the MTTRs (Memory-Type-Range Registers) from the main CPU.
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* There is also an ap_count which each AP increments as it starts up, so the
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* BSP can tell how many checked in.
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*
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* The APs are started with a SIPI (Startup Inter-Processor Interrupt) which
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* tells an AP to start executing at a particular address, in this case
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* AP_DEFAULT_BASE which contains the code copied from ap_start16. This protocol
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* is handled by start_aps().
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*
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* After being started, each AP runs the code in ap_start16, switches to 32-bit
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* mode, runs the code at ap_start, then jumps to c_handler which is ap_init().
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* This runs a very simple 'flight plan' described in mp_steps(). This sets up
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* the CPU and waits for further instructions by looking at its entry in
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* ap_callbacks[]. Note that the flight plan is only actually run for each CPU
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* in bsp_do_flight_plan(): once the BSP completes each flight record, it sets
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* mp_flight_record->barrier to 1 to allow the APs to executed the record one
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* by one.
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*
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* CPUS are numbered sequentially from 0 using the device tree:
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*
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* cpus {
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* u-boot,dm-pre-reloc;
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* #address-cells = <1>;
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* #size-cells = <0>;
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*
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* cpu@0 {
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* u-boot,dm-pre-reloc;
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* device_type = "cpu";
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* compatible = "intel,apl-cpu";
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* reg = <0>;
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* intel,apic-id = <0>;
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* };
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*
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* cpu@1 {
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* device_type = "cpu";
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* compatible = "intel,apl-cpu";
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* reg = <1>;
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* intel,apic-id = <2>;
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* };
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*
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* Here the 'reg' property is the CPU number and then is placed in dev->req_seq
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* so that we can index into ap_callbacks[] using that. The APIC ID is different
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* and may not be sequential (it typically is if hyperthreading is supported).
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*
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* Once APs are inited they wait in ap_wait_for_instruction() for instructions.
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* Instructions come in the form of a function to run. This logic is in
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* mp_run_on_cpus() which supports running on any one AP, all APs, just the BSP
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* or all CPUs. The BSP logic is handled directly in mp_run_on_cpus(), by
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* calling the function. For the APs, callback information is stored in a
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* single, common struct mp_callback and a pointer to this is written to each
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* AP's slot in ap_callbacks[] by run_ap_work(). All APs get the message even
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* if it is only for one of them. When an AP notices a message it checks whether
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* it should call the function (see check in ap_wait_for_instruction()) and then
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* does so if needed. After that it sets its slot to NULL to indicate it is
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* done.
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*
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* While U-Boot is running it can use mp_run_on_cpus() to run code on the APs.
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* An example of this is the 'mtrr' command which allows reading and changing
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* the MTRRs on all CPUs.
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*
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* Before U-Boot exits it calls mp_park_aps() which tells all CPUs to halt by
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* executing a 'hlt' instruction. That allows them to be used by Linux when it
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* starts up.
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*/
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/* This also needs to match the sipi.S assembly code for saved MSR encoding */
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struct __packed saved_msr {
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uint32_t index;
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uint32_t lo;
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uint32_t hi;
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};
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/**
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* struct mp_flight_plan - Holds the flight plan
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*
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* @num_records: Number of flight records
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* @records: Pointer to each record
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*/
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struct mp_flight_plan {
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int num_records;
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struct mp_flight_record *records;
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};
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/**
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* struct mp_callback - Callback information for APs
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*
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* @func: Function to run
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* @arg: Argument to pass to the function
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* @logical_cpu_number: Either a CPU number (i.e. dev->req_seq) or a special
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* value like MP_SELECT_BSP. It tells the AP whether it should process this
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* callback
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*/
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struct mp_callback {
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mp_run_func func;
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void *arg;
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int logical_cpu_number;
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};
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/* Stores the flight plan so that APs can find it */
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static struct mp_flight_plan mp_info;
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/*
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* ap_callbacks - Callback mailbox array
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*
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* Array of callback, one entry for each available CPU, indexed by the CPU
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* number, which is dev->req_seq. The entry for the main CPU is never used.
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* When this is NULL, there is no pending work for the CPU to run. When
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* non-NULL it points to the mp_callback structure. This is shared between all
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* CPUs, so should only be written by the main CPU.
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*/
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static struct mp_callback **ap_callbacks;
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static inline void barrier_wait(atomic_t *b)
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{
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while (atomic_read(b) == 0)
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asm("pause");
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mfence();
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}
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static inline void release_barrier(atomic_t *b)
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{
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mfence();
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atomic_set(b, 1);
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}
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static inline void stop_this_cpu(void)
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{
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/* Called by an AP when it is ready to halt and wait for a new task */
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for (;;)
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cpu_hlt();
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}
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/* Returns 1 if timeout waiting for APs. 0 if target APs found */
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static int wait_for_aps(atomic_t *val, int target, int total_delay,
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int delay_step)
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{
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int timeout = 0;
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int delayed = 0;
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while (atomic_read(val) != target) {
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udelay(delay_step);
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delayed += delay_step;
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if (delayed >= total_delay) {
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timeout = 1;
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break;
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}
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}
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return timeout;
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}
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static void ap_do_flight_plan(struct udevice *cpu)
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{
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int i;
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for (i = 0; i < mp_info.num_records; i++) {
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struct mp_flight_record *rec = &mp_info.records[i];
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atomic_inc(&rec->cpus_entered);
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barrier_wait(&rec->barrier);
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if (rec->ap_call != NULL)
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rec->ap_call(cpu, rec->ap_arg);
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}
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}
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static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
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{
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struct udevice *dev;
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*devp = NULL;
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for (uclass_find_first_device(UCLASS_CPU, &dev);
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dev;
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uclass_find_next_device(&dev)) {
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struct cpu_platdata *plat = dev_get_parent_platdata(dev);
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if (plat->cpu_id == apic_id) {
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*devp = dev;
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return 0;
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}
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}
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return -ENOENT;
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}
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/*
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* By the time APs call ap_init() caching has been setup, and microcode has
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* been loaded
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*/
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static void ap_init(unsigned int cpu_index)
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{
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struct udevice *dev;
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int apic_id;
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int ret;
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/* Ensure the local apic is enabled */
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enable_lapic();
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apic_id = lapicid();
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ret = find_cpu_by_apic_id(apic_id, &dev);
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if (ret) {
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debug("Unknown CPU apic_id %x\n", apic_id);
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goto done;
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}
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debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
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dev ? dev->name : "(apic_id not found)");
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/*
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* Walk the flight plan, which only returns if CONFIG_SMP_AP_WORK is not
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* enabled
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*/
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ap_do_flight_plan(dev);
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done:
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stop_this_cpu();
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}
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static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
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MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
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MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
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MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
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MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
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};
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static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
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{
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msr_t msr;
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msr = msr_read(index);
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entry->index = index;
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entry->lo = msr.lo;
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entry->hi = msr.hi;
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/* Return the next entry */
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entry++;
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return entry;
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}
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static int save_bsp_msrs(char *start, int size)
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{
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int msr_count;
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int num_var_mtrrs;
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struct saved_msr *msr_entry;
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int i;
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msr_t msr;
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/* Determine number of MTRRs need to be saved */
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msr = msr_read(MTRR_CAP_MSR);
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num_var_mtrrs = msr.lo & 0xff;
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/* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
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msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
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if ((msr_count * sizeof(struct saved_msr)) > size) {
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printf("Cannot mirror all %d msrs\n", msr_count);
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return -ENOSPC;
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}
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msr_entry = (void *)start;
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for (i = 0; i < NUM_FIXED_MTRRS; i++)
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msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
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for (i = 0; i < num_var_mtrrs; i++) {
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msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
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msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
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}
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msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
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return msr_count;
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}
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static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
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{
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struct sipi_params_16bit *params16;
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struct sipi_params *params;
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static char msr_save[512];
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char *stack;
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ulong addr;
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int code_len;
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int size;
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int ret;
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/* Copy in the code */
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code_len = ap_start16_code_end - ap_start16;
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debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
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code_len);
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memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
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addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
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params16 = (struct sipi_params_16bit *)addr;
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params16->ap_start = (uint32_t)ap_start;
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params16->gdt = (uint32_t)gd->arch.gdt;
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params16->gdt_limit = X86_GDT_SIZE - 1;
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debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
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params = (struct sipi_params *)sipi_params;
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debug("SIPI 32-bit params at %p\n", params);
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params->idt_ptr = (uint32_t)x86_get_idt();
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params->stack_size = CONFIG_AP_STACK_SIZE;
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size = params->stack_size * num_cpus;
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stack = memalign(4096, size);
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if (!stack)
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return -ENOMEM;
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params->stack_top = (u32)(stack + size);
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#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
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!defined(CONFIG_INTEL_MID)
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params->microcode_ptr = ucode_base;
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debug("Microcode at %x\n", params->microcode_ptr);
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#endif
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params->msr_table_ptr = (u32)msr_save;
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ret = save_bsp_msrs(msr_save, sizeof(msr_save));
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if (ret < 0)
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return ret;
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params->msr_count = ret;
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params->c_handler = (uint32_t)&ap_init;
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*ap_countp = ¶ms->ap_count;
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atomic_set(*ap_countp, 0);
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debug("SIPI vector is ready\n");
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return 0;
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}
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static int check_cpu_devices(int expected_cpus)
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{
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int i;
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for (i = 0; i < expected_cpus; i++) {
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struct udevice *dev;
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int ret;
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ret = uclass_find_device(UCLASS_CPU, i, &dev);
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if (ret) {
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debug("Cannot find CPU %d in device tree\n", i);
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return ret;
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}
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}
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return 0;
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}
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/* Returns 1 for timeout. 0 on success */
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static int apic_wait_timeout(int total_delay, const char *msg)
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{
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int total = 0;
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if (!(lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY))
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return 0;
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debug("Waiting for %s...", msg);
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while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
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udelay(50);
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total += 50;
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if (total >= total_delay) {
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debug("timed out: aborting\n");
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return -ETIMEDOUT;
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}
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}
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debug("done\n");
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return 0;
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}
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/**
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* start_aps() - Start up the APs and count how many we find
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*
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* This is called on the boot processor to start up all the other processors
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* (here called APs).
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*
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* @num_aps: Number of APs we expect to find
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* @ap_count: Initially zero. Incremented by this function for each AP found
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* @return 0 if all APs were set up correctly or there are none to set up,
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* -ENOSPC if the SIPI vector is too high in memory,
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* -ETIMEDOUT if the ICR is busy or the second SIPI fails to complete
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* -EIO if not all APs check in correctly
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*/
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static int start_aps(int num_aps, atomic_t *ap_count)
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{
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int sipi_vector;
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/* Max location is 4KiB below 1MiB */
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const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
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if (num_aps == 0)
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return 0;
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/* The vector is sent as a 4k aligned address in one byte */
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sipi_vector = AP_DEFAULT_BASE >> 12;
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if (sipi_vector > max_vector_loc) {
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printf("SIPI vector too large! 0x%08x\n",
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sipi_vector);
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return -ENOSPC;
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}
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debug("Attempting to start %d APs\n", num_aps);
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if (apic_wait_timeout(1000, "ICR not to be busy"))
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return -ETIMEDOUT;
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/* Send INIT IPI to all but self */
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_INIT);
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debug("Waiting for 10ms after sending INIT\n");
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mdelay(10);
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/* Send 1st SIPI */
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if (apic_wait_timeout(1000, "ICR not to be busy"))
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return -ETIMEDOUT;
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_STARTUP | sipi_vector);
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if (apic_wait_timeout(10000, "first SIPI to complete"))
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return -ETIMEDOUT;
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/* Wait for CPUs to check in up to 200 us */
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wait_for_aps(ap_count, num_aps, 200, 15);
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/* Send 2nd SIPI */
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if (apic_wait_timeout(1000, "ICR not to be busy"))
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return -ETIMEDOUT;
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
|
|
LAPIC_DM_STARTUP | sipi_vector);
|
|
if (apic_wait_timeout(10000, "second SIPI to complete"))
|
|
return -ETIMEDOUT;
|
|
|
|
/* Wait for CPUs to check in */
|
|
if (wait_for_aps(ap_count, num_aps, 10000, 50)) {
|
|
debug("Not all APs checked in: %d/%d\n",
|
|
atomic_read(ap_count), num_aps);
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* bsp_do_flight_plan() - Do the flight plan on the BSP
|
|
*
|
|
* This runs the flight plan on the main CPU used to boot U-Boot
|
|
*
|
|
* @cpu: Device for the main CPU
|
|
* @plan: Flight plan to run
|
|
* @num_aps: Number of APs (CPUs other than the BSP)
|
|
* @returns 0 on success, -ETIMEDOUT if an AP failed to come up
|
|
*/
|
|
static int bsp_do_flight_plan(struct udevice *cpu, struct mp_flight_plan *plan,
|
|
int num_aps)
|
|
{
|
|
int i;
|
|
int ret = 0;
|
|
const int timeout_us = 100000;
|
|
const int step_us = 100;
|
|
|
|
for (i = 0; i < plan->num_records; i++) {
|
|
struct mp_flight_record *rec = &plan->records[i];
|
|
|
|
/* Wait for APs if the record is not released */
|
|
if (atomic_read(&rec->barrier) == 0) {
|
|
/* Wait for the APs to check in */
|
|
if (wait_for_aps(&rec->cpus_entered, num_aps,
|
|
timeout_us, step_us)) {
|
|
debug("MP record %d timeout\n", i);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
}
|
|
|
|
if (rec->bsp_call != NULL)
|
|
rec->bsp_call(cpu, rec->bsp_arg);
|
|
|
|
release_barrier(&rec->barrier);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* get_bsp() - Get information about the bootstrap processor
|
|
*
|
|
* @devp: If non-NULL, returns CPU device corresponding to the BSP
|
|
* @cpu_countp: If non-NULL, returns the total number of CPUs
|
|
* @return CPU number of the BSP, or -ve on error. If multiprocessing is not
|
|
* enabled, returns 0
|
|
*/
|
|
static int get_bsp(struct udevice **devp, int *cpu_countp)
|
|
{
|
|
char processor_name[CPU_MAX_NAME_LEN];
|
|
struct udevice *dev;
|
|
int apic_id;
|
|
int ret;
|
|
|
|
cpu_get_name(processor_name);
|
|
debug("CPU: %s\n", processor_name);
|
|
|
|
apic_id = lapicid();
|
|
ret = find_cpu_by_apic_id(apic_id, &dev);
|
|
if (ret < 0) {
|
|
printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
|
|
return ret;
|
|
}
|
|
ret = cpu_get_count(dev);
|
|
if (ret < 0)
|
|
return log_msg_ret("count", ret);
|
|
if (devp)
|
|
*devp = dev;
|
|
if (cpu_countp)
|
|
*cpu_countp = ret;
|
|
|
|
return dev->req_seq >= 0 ? dev->req_seq : 0;
|
|
}
|
|
|
|
/**
|
|
* read_callback() - Read the pointer in a callback slot
|
|
*
|
|
* This is called by APs to read their callback slot to see if there is a
|
|
* pointer to new instructions
|
|
*
|
|
* @slot: Pointer to the AP's callback slot
|
|
* @return value of that pointer
|
|
*/
|
|
static struct mp_callback *read_callback(struct mp_callback **slot)
|
|
{
|
|
dmb();
|
|
|
|
return *slot;
|
|
}
|
|
|
|
/**
|
|
* store_callback() - Store a pointer to the callback slot
|
|
*
|
|
* This is called by APs to write NULL into the callback slot when they have
|
|
* finished the work requested by the BSP.
|
|
*
|
|
* @slot: Pointer to the AP's callback slot
|
|
* @val: Value to write (e.g. NULL)
|
|
*/
|
|
static void store_callback(struct mp_callback **slot, struct mp_callback *val)
|
|
{
|
|
*slot = val;
|
|
dmb();
|
|
}
|
|
|
|
/**
|
|
* run_ap_work() - Run a callback on selected APs
|
|
*
|
|
* This writes @callback to all APs and waits for them all to acknowledge it,
|
|
* Note that whether each AP actually calls the callback depends on the value
|
|
* of logical_cpu_number (see struct mp_callback). The logical CPU number is
|
|
* the CPU device's req->seq value.
|
|
*
|
|
* @callback: Callback information to pass to all APs
|
|
* @bsp: CPU device for the BSP
|
|
* @num_cpus: The number of CPUs in the system (= number of APs + 1)
|
|
* @expire_ms: Timeout to wait for all APs to finish, in milliseconds, or 0 for
|
|
* no timeout
|
|
* @return 0 if OK, -ETIMEDOUT if one or more APs failed to respond in time
|
|
*/
|
|
static int run_ap_work(struct mp_callback *callback, struct udevice *bsp,
|
|
int num_cpus, uint expire_ms)
|
|
{
|
|
int cur_cpu = bsp->req_seq;
|
|
int num_aps = num_cpus - 1; /* number of non-BSPs to get this message */
|
|
int cpus_accepted;
|
|
ulong start;
|
|
int i;
|
|
|
|
if (!IS_ENABLED(CONFIG_SMP_AP_WORK)) {
|
|
printf("APs already parked. CONFIG_SMP_AP_WORK not enabled\n");
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
/* Signal to all the APs to run the func. */
|
|
for (i = 0; i < num_cpus; i++) {
|
|
if (cur_cpu != i)
|
|
store_callback(&ap_callbacks[i], callback);
|
|
}
|
|
mfence();
|
|
|
|
/* Wait for all the APs to signal back that call has been accepted. */
|
|
start = get_timer(0);
|
|
|
|
do {
|
|
mdelay(1);
|
|
cpus_accepted = 0;
|
|
|
|
for (i = 0; i < num_cpus; i++) {
|
|
if (cur_cpu == i)
|
|
continue;
|
|
if (!read_callback(&ap_callbacks[i]))
|
|
cpus_accepted++;
|
|
}
|
|
|
|
if (expire_ms && get_timer(start) >= expire_ms) {
|
|
log(UCLASS_CPU, LOGL_CRIT,
|
|
"AP call expired; %d/%d CPUs accepted\n",
|
|
cpus_accepted, num_aps);
|
|
return -ETIMEDOUT;
|
|
}
|
|
} while (cpus_accepted != num_aps);
|
|
|
|
/* Make sure we can see any data written by the APs */
|
|
mfence();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ap_wait_for_instruction() - Wait for and process requests from the main CPU
|
|
*
|
|
* This is called by APs (here, everything other than the main boot CPU) to
|
|
* await instructions. They arrive in the form of a function call and argument,
|
|
* which is then called. This uses a simple mailbox with atomic read/set
|
|
*
|
|
* @cpu: CPU that is waiting
|
|
* @unused: Optional argument provided by struct mp_flight_record, not used here
|
|
* @return Does not return
|
|
*/
|
|
static int ap_wait_for_instruction(struct udevice *cpu, void *unused)
|
|
{
|
|
struct mp_callback lcb;
|
|
struct mp_callback **per_cpu_slot;
|
|
|
|
if (!IS_ENABLED(CONFIG_SMP_AP_WORK))
|
|
return 0;
|
|
|
|
per_cpu_slot = &ap_callbacks[cpu->req_seq];
|
|
|
|
while (1) {
|
|
struct mp_callback *cb = read_callback(per_cpu_slot);
|
|
|
|
if (!cb) {
|
|
asm ("pause");
|
|
continue;
|
|
}
|
|
|
|
/* Copy to local variable before using the value */
|
|
memcpy(&lcb, cb, sizeof(lcb));
|
|
mfence();
|
|
if (lcb.logical_cpu_number == MP_SELECT_ALL ||
|
|
lcb.logical_cpu_number == MP_SELECT_APS ||
|
|
cpu->req_seq == lcb.logical_cpu_number)
|
|
lcb.func(lcb.arg);
|
|
|
|
/* Indicate we are finished */
|
|
store_callback(per_cpu_slot, NULL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mp_init_cpu(struct udevice *cpu, void *unused)
|
|
{
|
|
struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
|
|
|
|
plat->ucode_version = microcode_read_rev();
|
|
plat->device_id = gd->arch.x86_device;
|
|
|
|
return device_probe(cpu);
|
|
}
|
|
|
|
static struct mp_flight_record mp_steps[] = {
|
|
MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
|
|
MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL, NULL, NULL),
|
|
};
|
|
|
|
int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg)
|
|
{
|
|
struct mp_callback lcb = {
|
|
.func = func,
|
|
.arg = arg,
|
|
.logical_cpu_number = cpu_select,
|
|
};
|
|
struct udevice *dev;
|
|
int num_cpus;
|
|
int ret;
|
|
|
|
ret = get_bsp(&dev, &num_cpus);
|
|
if (ret < 0)
|
|
return log_msg_ret("bsp", ret);
|
|
if (cpu_select == MP_SELECT_ALL || cpu_select == MP_SELECT_BSP ||
|
|
cpu_select == ret) {
|
|
/* Run on BSP first */
|
|
func(arg);
|
|
}
|
|
|
|
if (!IS_ENABLED(CONFIG_SMP_AP_WORK) ||
|
|
!(gd->flags & GD_FLG_SMP_READY)) {
|
|
/* Allow use of this function on the BSP only */
|
|
if (cpu_select == MP_SELECT_BSP || !cpu_select)
|
|
return 0;
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
/* Allow up to 1 second for all APs to finish */
|
|
ret = run_ap_work(&lcb, dev, num_cpus, 1000 /* ms */);
|
|
if (ret)
|
|
return log_msg_ret("aps", ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void park_this_cpu(void *unused)
|
|
{
|
|
stop_this_cpu();
|
|
}
|
|
|
|
int mp_park_aps(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = mp_run_on_cpus(MP_SELECT_APS, park_this_cpu, NULL);
|
|
if (ret)
|
|
return log_ret(ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mp_first_cpu(int cpu_select)
|
|
{
|
|
struct udevice *dev;
|
|
int num_cpus;
|
|
int ret;
|
|
|
|
/*
|
|
* This assumes that CPUs are numbered from 0. This function tries to
|
|
* avoid assuming the CPU 0 is the boot CPU
|
|
*/
|
|
if (cpu_select == MP_SELECT_ALL)
|
|
return 0; /* start with the first one */
|
|
|
|
ret = get_bsp(&dev, &num_cpus);
|
|
if (ret < 0)
|
|
return log_msg_ret("bsp", ret);
|
|
|
|
/* Return boot CPU if requested */
|
|
if (cpu_select == MP_SELECT_BSP)
|
|
return ret;
|
|
|
|
/* Return something other than the boot CPU, if APs requested */
|
|
if (cpu_select == MP_SELECT_APS && num_cpus > 1)
|
|
return ret == 0 ? 1 : 0;
|
|
|
|
/* Try to check for an invalid value */
|
|
if (cpu_select < 0 || cpu_select >= num_cpus)
|
|
return -EINVAL;
|
|
|
|
return cpu_select; /* return the only selected one */
|
|
}
|
|
|
|
int mp_next_cpu(int cpu_select, int prev_cpu)
|
|
{
|
|
struct udevice *dev;
|
|
int num_cpus;
|
|
int ret;
|
|
int bsp;
|
|
|
|
/* If we selected the BSP or a particular single CPU, we are done */
|
|
if (!IS_ENABLED(CONFIG_SMP_AP_WORK) || cpu_select == MP_SELECT_BSP ||
|
|
cpu_select >= 0)
|
|
return -EFBIG;
|
|
|
|
/* Must be doing MP_SELECT_ALL or MP_SELECT_APS; return the next CPU */
|
|
ret = get_bsp(&dev, &num_cpus);
|
|
if (ret < 0)
|
|
return log_msg_ret("bsp", ret);
|
|
bsp = ret;
|
|
|
|
/* Move to the next CPU */
|
|
assert(prev_cpu >= 0);
|
|
ret = prev_cpu + 1;
|
|
|
|
/* Skip the BSP if needed */
|
|
if (cpu_select == MP_SELECT_APS && ret == bsp)
|
|
ret++;
|
|
if (ret >= num_cpus)
|
|
return -EFBIG;
|
|
|
|
return ret;
|
|
}
|
|
|
|
int mp_init(void)
|
|
{
|
|
int num_aps, num_cpus;
|
|
atomic_t *ap_count;
|
|
struct udevice *cpu;
|
|
struct uclass *uc;
|
|
int ret;
|
|
|
|
if (IS_ENABLED(CONFIG_QFW)) {
|
|
ret = qemu_cpu_fixup();
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Multiple APs are brought up simultaneously and they may get the same
|
|
* seq num in the uclass_resolve_seq() during device_probe(). To avoid
|
|
* this, set req_seq to the reg number in the device tree in advance.
|
|
*/
|
|
uclass_id_foreach_dev(UCLASS_CPU, cpu, uc)
|
|
cpu->req_seq = dev_read_u32_default(cpu, "reg", -1);
|
|
|
|
ret = get_bsp(&cpu, &num_cpus);
|
|
if (ret < 0) {
|
|
debug("Cannot init boot CPU: err=%d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
if (num_cpus < 2)
|
|
debug("Warning: Only 1 CPU is detected\n");
|
|
|
|
ret = check_cpu_devices(num_cpus);
|
|
if (ret)
|
|
log_warning("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
|
|
|
|
ap_callbacks = calloc(num_cpus, sizeof(struct mp_callback *));
|
|
if (!ap_callbacks)
|
|
return -ENOMEM;
|
|
|
|
/* Copy needed parameters so that APs have a reference to the plan */
|
|
mp_info.num_records = ARRAY_SIZE(mp_steps);
|
|
mp_info.records = mp_steps;
|
|
|
|
/* Load the SIPI vector */
|
|
ret = load_sipi_vector(&ap_count, num_cpus);
|
|
if (ap_count == NULL)
|
|
return -ENOENT;
|
|
|
|
/*
|
|
* Make sure SIPI data hits RAM so the APs that come up will see
|
|
* the startup code even if the caches are disabled
|
|
*/
|
|
wbinvd();
|
|
|
|
/* Start the APs providing number of APs and the cpus_entered field */
|
|
num_aps = num_cpus - 1;
|
|
ret = start_aps(num_aps, ap_count);
|
|
if (ret) {
|
|
mdelay(1000);
|
|
debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
|
|
num_aps);
|
|
return ret;
|
|
}
|
|
|
|
/* Walk the flight plan for the BSP */
|
|
ret = bsp_do_flight_plan(cpu, &mp_info, num_aps);
|
|
if (ret) {
|
|
debug("CPU init failed: err=%d\n", ret);
|
|
return ret;
|
|
}
|
|
gd->flags |= GD_FLG_SMP_READY;
|
|
|
|
return 0;
|
|
}
|