mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-26 21:03:44 +09:00
ba6a169811
Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
20 lines
433 B
C
20 lines
433 B
C
#ifndef __GIC_V2_H__
|
|
#define __GIC_V2_H__
|
|
|
|
/* register offsets for the ARM generic interrupt controller (GIC) */
|
|
|
|
#define GIC_DIST_OFFSET 0x1000
|
|
#define GICD_CTLR 0x0000
|
|
#define GICD_TYPER 0x0004
|
|
#define GICD_IGROUPRn 0x0080
|
|
#define GICD_SGIR 0x0F00
|
|
|
|
#define GIC_CPU_OFFSET_A9 0x0100
|
|
#define GIC_CPU_OFFSET_A15 0x2000
|
|
#define GICC_CTLR 0x0000
|
|
#define GICC_PMR 0x0004
|
|
#define GICC_IAR 0x000C
|
|
#define GICC_EOIR 0x0010
|
|
|
|
#endif
|