mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 07:06:19 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
153 lines
3.5 KiB
C
153 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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#include "../sg-regs.h"
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#include "pll.h"
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static void upll_init(void)
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{
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u32 tmp, clk_mode_upll, clk_mode_axosel;
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tmp = readl(SG_PINMON0);
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clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
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clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
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/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
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tmp = readl(SC_UPLLCTRL);
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tmp &= ~0x18000000;
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writel(tmp, SC_UPLLCTRL);
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if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
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/* AXO: 25MHz */
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tmp &= ~0x07ffffff;
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tmp |= 0x0228f5c0;
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} else {
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/* AXO: default 24.576MHz */
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tmp &= ~0x07ffffff;
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tmp |= 0x02328000;
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}
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}
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writel(tmp, SC_UPLLCTRL);
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/* set 1 to K_LD(UPLLCTRL.bit[27]) */
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tmp |= 0x08000000;
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writel(tmp, SC_UPLLCTRL);
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/* wait 10 usec */
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udelay(10);
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/* set 1 to SNRT(UPLLCTRL.bit[28]) */
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tmp |= 0x10000000;
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writel(tmp, SC_UPLLCTRL);
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}
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static void vpll_init(void)
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{
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u32 tmp, clk_mode_axosel;
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tmp = readl(SG_PINMON0);
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clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
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/* set 1 to VPLA27WP and VPLA27WP */
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tmp = readl(SC_VPLL27ACTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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/* Set 0 to VPLA_K_LD and VPLB_K_LD */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* Set 0 to VPLA_SNRST and VPLB_SNRST */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27BCTRL2);
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/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27BCTRL2);
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
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/* AXO: 25MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066664;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066664;
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writel(tmp, SC_VPLL27BCTRL3);
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} else {
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/* AXO: default 24.576MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27BCTRL3);
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}
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/* Set 1 to VPLA_K_LD and VPLB_K_LD */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* wait 10 usec */
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udelay(10);
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/* Set 0 to VPLA_SNRST and VPLB_SNRST */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL2);
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/* set 0 to VPLA27WP and VPLA27WP */
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tmp = readl(SC_VPLL27ACTRL);
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tmp &= ~0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp |= ~0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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}
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void uniphier_ld4_pll_init(void)
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{
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upll_init();
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vpll_init();
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uniphier_ld4_dpll_ssc_en();
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}
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