mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 11:46:17 +09:00
ea273e8d72
Both the RAVB and SH ether driver now support parsing the PHY reset GPIOs from both the PHY nodes and the MAC nodes, move the reset GPIOs back into the PHY nodes to minimize DT difference between U-Boot and Linux. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
124 lines
2.1 KiB
Plaintext
124 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Eagle board
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*
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* Copyright (C) 2016-2017 Renesas Electronics Corp.
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* Copyright (C) 2017 Cogent Embedded, Inc.
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*/
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/dts-v1/;
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#include "r8a77970.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Renesas Eagle board based on r8a77970";
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compatible = "renesas,eagle", "renesas,r8a77970";
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aliases {
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serial0 = &scif0;
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ethernet0 = &avb;
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spi0 = &rpc;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x38000000>;
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};
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};
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&avb {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio1>;
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interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
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};
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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io_expander: gpio@20 {
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compatible = "onnn,pca9654";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&pfc {
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avb0_pins: avb {
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mux {
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groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
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function = "avb0";
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};
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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scif0_pins: scif0 {
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groups = "scif0_data";
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function = "scif0";
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};
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};
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&rpc {
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num-cs = <1>;
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status = "okay";
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash0: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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reg = <0>;
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status = "okay";
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};
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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