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https://github.com/brain-hackers/u-boot-brain
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![Jernej Skrabec](/assets/img/avatar_default.png)
Designware HDMI controller and phy are used in other SoCs as well. Split out platform independent code. DW HDMI has 8 bit registers but they can be represented as 32 bit registers as well. Add support to select access mode. EDID reading code use reading by blocks which is not supported by other SoCs in general. Make it more general using byte by byte approach, which is also used in Linux driver. Finally, not all DW HDMI controllers are accompanied with DW HDMI phy. Support custom phys by making controller code independent from phy code. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Tested-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
187 lines
4.3 KiB
C
187 lines
4.3 KiB
C
/*
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <dw_hdmi.h>
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#include <edid.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/grf_rk3288.h>
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#include <power/regulator.h>
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struct rk_hdmi_priv {
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struct dw_hdmi hdmi;
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struct rk3288_grf *grf;
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};
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static const struct hdmi_phy_config rockchip_phy_config[] = {
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{
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.mpixelclock = 74250000,
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.sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
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}, {
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.mpixelclock = 148500000,
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.sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
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}, {
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.mpixelclock = 297000000,
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.sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
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}, {
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.mpixelclock = ~0ul,
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.sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
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}
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};
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static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
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{
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.mpixelclock = 40000000,
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.cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
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}, {
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.mpixelclock = 65000000,
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.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
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}, {
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.mpixelclock = 66000000,
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.cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
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}, {
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.mpixelclock = 83500000,
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.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
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}, {
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.mpixelclock = 146250000,
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.cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
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}, {
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.mpixelclock = 148500000,
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.cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
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}, {
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.mpixelclock = ~0ul,
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.cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
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}
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};
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static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
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}
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static int rk_hdmi_enable(struct udevice *dev, int panel_bpp,
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const struct display_timing *edid)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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return dw_hdmi_enable(&priv->hdmi, edid);
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}
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static int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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struct dw_hdmi *hdmi = &priv->hdmi;
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hdmi->ioaddr = (ulong)dev_get_addr(dev);
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hdmi->mpll_cfg = rockchip_mpll_cfg;
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hdmi->phy_cfg = rockchip_phy_config;
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hdmi->i2c_clk_high = 0x7a;
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hdmi->i2c_clk_low = 0x8d;
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/*
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* TODO(sjg@chromium.org): The above values don't work - these ones
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* work better, but generate lots of errors in the data.
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*/
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hdmi->i2c_clk_high = 0x0d;
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hdmi->i2c_clk_low = 0x0d;
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hdmi->reg_io_width = 4;
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hdmi->phy_set = dw_hdmi_phy_cfg;
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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return 0;
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}
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static int rk_hdmi_probe(struct udevice *dev)
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{
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struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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struct dw_hdmi *hdmi = &priv->hdmi;
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struct udevice *reg;
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struct clk clk;
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int ret;
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int vop_id = uc_plat->source_id;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret >= 0) {
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ret = clk_set_rate(&clk, 0);
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clk_free(&clk);
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}
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if (ret) {
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debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret);
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return ret;
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}
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/*
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* Configure the maximum clock to permit whatever resolution the
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* monitor wants
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*/
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ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
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if (ret >= 0) {
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ret = clk_set_rate(&clk, 384000000);
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clk_free(&clk);
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}
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if (ret < 0) {
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debug("%s: Failed to set clock in source device '%s': ret=%d\n",
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__func__, uc_plat->src_dev->name, ret);
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return ret;
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}
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ret = regulator_get_by_platname("vcc50_hdmi", ®);
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if (!ret)
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ret = regulator_set_enable(reg, true);
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if (ret)
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debug("%s: Cannot set regulator vcc50_hdmi\n", __func__);
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/* hdmi source select hdmi controller */
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rk_setreg(&priv->grf->soc_con6, 1 << 15);
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/* hdmi data from vop id */
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rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
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(vop_id == 1) ? (1 << 4) : 0);
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ret = dw_hdmi_phy_wait_for_hpd(hdmi);
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if (ret < 0) {
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debug("hdmi can not get hpd signal\n");
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return -1;
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}
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dw_hdmi_init(hdmi);
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dw_hdmi_phy_init(hdmi);
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return 0;
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}
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static const struct dm_display_ops rk_hdmi_ops = {
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.read_edid = rk_hdmi_read_edid,
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.enable = rk_hdmi_enable,
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};
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static const struct udevice_id rk_hdmi_ids[] = {
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{ .compatible = "rockchip,rk3288-dw-hdmi" },
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{ }
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};
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U_BOOT_DRIVER(hdmi_rockchip) = {
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.name = "hdmi_rockchip",
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.id = UCLASS_DISPLAY,
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.of_match = rk_hdmi_ids,
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.ops = &rk_hdmi_ops,
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.ofdata_to_platdata = rk_hdmi_ofdata_to_platdata,
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.probe = rk_hdmi_probe,
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.priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
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};
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