842 lines
22 KiB
C
842 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <clk.h>
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#include <ram.h>
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#include <reset.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <linux/iopoll.h>
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#include "stm32mp1_ddr.h"
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#include "stm32mp1_ddr_regs.h"
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#define RCC_DDRITFCR 0xD8
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#define RCC_DDRITFCR_DDRCAPBRST (BIT(14))
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#define RCC_DDRITFCR_DDRCAXIRST (BIT(15))
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#define RCC_DDRITFCR_DDRCORERST (BIT(16))
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#define RCC_DDRITFCR_DPHYAPBRST (BIT(17))
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#define RCC_DDRITFCR_DPHYRST (BIT(18))
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#define RCC_DDRITFCR_DPHYCTLRST (BIT(19))
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struct reg_desc {
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const char *name;
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u16 offset; /* offset for base address */
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u8 par_offset; /* offset for parameter array */
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};
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#define INVALID_OFFSET 0xFF
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#define DDRCTL_REG(x, y) \
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{#x,\
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offsetof(struct stm32mp1_ddrctl, x),\
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offsetof(struct y, x)}
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#define DDRPHY_REG(x, y) \
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{#x,\
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offsetof(struct stm32mp1_ddrphy, x),\
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offsetof(struct y, x)}
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#define DDR_REG_DYN(x) \
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{#x,\
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offsetof(struct stm32mp1_ddrctl, x),\
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INVALID_OFFSET}
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#define DDRPHY_REG_DYN(x) \
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{#x,\
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offsetof(struct stm32mp1_ddrphy, x),\
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INVALID_OFFSET}
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/***********************************************************
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* PARAMETERS: value get from device tree :
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* size / order need to be aligned with binding
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* modification NOT ALLOWED !!!
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***********************************************************/
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#define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */
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#define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */
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#define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */
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#define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */
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#define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
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#define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
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#define DDRPHY_REG_CAL_SIZE 12 /* st,phy-cal */
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#define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
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static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
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DDRCTL_REG_REG(mstr),
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DDRCTL_REG_REG(mrctrl0),
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DDRCTL_REG_REG(mrctrl1),
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DDRCTL_REG_REG(derateen),
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DDRCTL_REG_REG(derateint),
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DDRCTL_REG_REG(pwrctl),
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DDRCTL_REG_REG(pwrtmg),
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DDRCTL_REG_REG(hwlpctl),
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DDRCTL_REG_REG(rfshctl0),
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DDRCTL_REG_REG(rfshctl3),
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DDRCTL_REG_REG(crcparctl0),
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DDRCTL_REG_REG(zqctl0),
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DDRCTL_REG_REG(dfitmg0),
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DDRCTL_REG_REG(dfitmg1),
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DDRCTL_REG_REG(dfilpcfg0),
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DDRCTL_REG_REG(dfiupd0),
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DDRCTL_REG_REG(dfiupd1),
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DDRCTL_REG_REG(dfiupd2),
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DDRCTL_REG_REG(dfiphymstr),
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DDRCTL_REG_REG(odtmap),
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DDRCTL_REG_REG(dbg0),
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DDRCTL_REG_REG(dbg1),
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DDRCTL_REG_REG(dbgcmd),
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DDRCTL_REG_REG(poisoncfg),
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DDRCTL_REG_REG(pccfg),
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};
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#define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
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static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
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DDRCTL_REG_TIMING(rfshtmg),
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DDRCTL_REG_TIMING(dramtmg0),
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DDRCTL_REG_TIMING(dramtmg1),
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DDRCTL_REG_TIMING(dramtmg2),
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DDRCTL_REG_TIMING(dramtmg3),
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DDRCTL_REG_TIMING(dramtmg4),
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DDRCTL_REG_TIMING(dramtmg5),
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DDRCTL_REG_TIMING(dramtmg6),
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DDRCTL_REG_TIMING(dramtmg7),
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DDRCTL_REG_TIMING(dramtmg8),
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DDRCTL_REG_TIMING(dramtmg14),
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DDRCTL_REG_TIMING(odtcfg),
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};
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#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map)
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static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
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DDRCTL_REG_MAP(addrmap1),
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DDRCTL_REG_MAP(addrmap2),
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DDRCTL_REG_MAP(addrmap3),
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DDRCTL_REG_MAP(addrmap4),
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DDRCTL_REG_MAP(addrmap5),
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DDRCTL_REG_MAP(addrmap6),
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DDRCTL_REG_MAP(addrmap9),
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DDRCTL_REG_MAP(addrmap10),
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DDRCTL_REG_MAP(addrmap11),
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};
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#define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
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static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
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DDRCTL_REG_PERF(sched),
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DDRCTL_REG_PERF(sched1),
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DDRCTL_REG_PERF(perfhpr1),
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DDRCTL_REG_PERF(perflpr1),
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DDRCTL_REG_PERF(perfwr1),
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DDRCTL_REG_PERF(pcfgr_0),
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DDRCTL_REG_PERF(pcfgw_0),
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DDRCTL_REG_PERF(pcfgqos0_0),
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DDRCTL_REG_PERF(pcfgqos1_0),
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DDRCTL_REG_PERF(pcfgwqos0_0),
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DDRCTL_REG_PERF(pcfgwqos1_0),
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DDRCTL_REG_PERF(pcfgr_1),
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DDRCTL_REG_PERF(pcfgw_1),
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DDRCTL_REG_PERF(pcfgqos0_1),
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DDRCTL_REG_PERF(pcfgqos1_1),
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DDRCTL_REG_PERF(pcfgwqos0_1),
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DDRCTL_REG_PERF(pcfgwqos1_1),
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};
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#define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
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static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
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DDRPHY_REG_REG(pgcr),
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DDRPHY_REG_REG(aciocr),
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DDRPHY_REG_REG(dxccr),
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DDRPHY_REG_REG(dsgcr),
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DDRPHY_REG_REG(dcr),
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DDRPHY_REG_REG(odtcr),
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DDRPHY_REG_REG(zq0cr1),
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DDRPHY_REG_REG(dx0gcr),
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DDRPHY_REG_REG(dx1gcr),
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DDRPHY_REG_REG(dx2gcr),
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DDRPHY_REG_REG(dx3gcr),
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};
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#define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
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static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
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DDRPHY_REG_TIMING(ptr0),
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DDRPHY_REG_TIMING(ptr1),
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DDRPHY_REG_TIMING(ptr2),
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DDRPHY_REG_TIMING(dtpr0),
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DDRPHY_REG_TIMING(dtpr1),
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DDRPHY_REG_TIMING(dtpr2),
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DDRPHY_REG_TIMING(mr0),
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DDRPHY_REG_TIMING(mr1),
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DDRPHY_REG_TIMING(mr2),
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DDRPHY_REG_TIMING(mr3),
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};
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#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
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static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = {
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DDRPHY_REG_CAL(dx0dllcr),
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DDRPHY_REG_CAL(dx0dqtr),
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DDRPHY_REG_CAL(dx0dqstr),
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DDRPHY_REG_CAL(dx1dllcr),
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DDRPHY_REG_CAL(dx1dqtr),
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DDRPHY_REG_CAL(dx1dqstr),
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DDRPHY_REG_CAL(dx2dllcr),
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DDRPHY_REG_CAL(dx2dqtr),
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DDRPHY_REG_CAL(dx2dqstr),
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DDRPHY_REG_CAL(dx3dllcr),
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DDRPHY_REG_CAL(dx3dqtr),
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DDRPHY_REG_CAL(dx3dqstr),
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};
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/**************************************************************
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* DYNAMIC REGISTERS: only used for debug purpose (read/modify)
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**************************************************************/
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#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
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static const struct reg_desc ddr_dyn[] = {
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DDR_REG_DYN(stat),
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DDR_REG_DYN(init0),
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DDR_REG_DYN(dfimisc),
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DDR_REG_DYN(dfistat),
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DDR_REG_DYN(swctl),
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DDR_REG_DYN(swstat),
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DDR_REG_DYN(pctrl_0),
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DDR_REG_DYN(pctrl_1),
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};
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#define DDR_REG_DYN_SIZE ARRAY_SIZE(ddr_dyn)
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static const struct reg_desc ddrphy_dyn[] = {
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DDRPHY_REG_DYN(pir),
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DDRPHY_REG_DYN(pgsr),
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DDRPHY_REG_DYN(zq0sr0),
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DDRPHY_REG_DYN(zq0sr1),
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DDRPHY_REG_DYN(dx0gsr0),
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DDRPHY_REG_DYN(dx0gsr1),
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DDRPHY_REG_DYN(dx1gsr0),
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DDRPHY_REG_DYN(dx1gsr1),
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DDRPHY_REG_DYN(dx2gsr0),
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DDRPHY_REG_DYN(dx2gsr1),
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DDRPHY_REG_DYN(dx3gsr0),
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DDRPHY_REG_DYN(dx3gsr1),
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};
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#define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn)
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#endif
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/*****************************************************************
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* REGISTERS ARRAY: used to parse device tree and interactive mode
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*****************************************************************/
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enum reg_type {
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REG_REG,
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REG_TIMING,
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REG_PERF,
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REG_MAP,
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REGPHY_REG,
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REGPHY_TIMING,
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REGPHY_CAL,
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#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
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/* dynamic registers => managed in driver or not changed,
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* can be dumped in interactive mode
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*/
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REG_DYN,
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REGPHY_DYN,
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#endif
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REG_TYPE_NB
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};
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enum base_type {
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DDR_BASE,
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DDRPHY_BASE,
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NONE_BASE
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};
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struct ddr_reg_info {
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const char *name;
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const struct reg_desc *desc;
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u8 size;
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enum base_type base;
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};
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#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
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const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
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[REG_REG] = {
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"static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
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[REG_TIMING] = {
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"timing", ddr_timing, DDRCTL_REG_TIMING_SIZE, DDR_BASE},
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[REG_PERF] = {
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"perf", ddr_perf, DDRCTL_REG_PERF_SIZE, DDR_BASE},
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[REG_MAP] = {
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"map", ddr_map, DDRCTL_REG_MAP_SIZE, DDR_BASE},
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[REGPHY_REG] = {
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"static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
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[REGPHY_TIMING] = {
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"timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
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[REGPHY_CAL] = {
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"cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE},
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#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
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[REG_DYN] = {
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"dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
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[REGPHY_DYN] = {
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"dyn", ddrphy_dyn, DDRPHY_REG_DYN_SIZE, DDRPHY_BASE},
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#endif
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};
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const char *base_name[] = {
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[DDR_BASE] = "ctl",
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[DDRPHY_BASE] = "phy",
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};
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static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
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{
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if (base == DDRPHY_BASE)
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return (u32)priv->phy;
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else
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return (u32)priv->ctl;
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}
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static void set_reg(const struct ddr_info *priv,
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enum reg_type type,
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const void *param)
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{
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unsigned int i;
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unsigned int *ptr, value;
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enum base_type base = ddr_registers[type].base;
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u32 base_addr = get_base_addr(priv, base);
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const struct reg_desc *desc = ddr_registers[type].desc;
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debug("init %s\n", ddr_registers[type].name);
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for (i = 0; i < ddr_registers[type].size; i++) {
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ptr = (unsigned int *)(base_addr + desc[i].offset);
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if (desc[i].par_offset == INVALID_OFFSET) {
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pr_err("invalid parameter offset for %s", desc[i].name);
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} else {
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value = *((u32 *)((u32)param +
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desc[i].par_offset));
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writel(value, ptr);
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debug("[0x%x] %s= 0x%08x\n",
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(u32)ptr, desc[i].name, value);
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}
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}
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}
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#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
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static void stm32mp1_dump_reg_desc(u32 base_addr, const struct reg_desc *desc)
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{
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unsigned int *ptr;
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ptr = (unsigned int *)(base_addr + desc->offset);
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printf("%s= 0x%08x\n", desc->name, readl(ptr));
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}
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static void stm32mp1_dump_param_desc(u32 par_addr, const struct reg_desc *desc)
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{
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unsigned int *ptr;
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ptr = (unsigned int *)(par_addr + desc->par_offset);
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printf("%s= 0x%08x\n", desc->name, readl(ptr));
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}
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static const struct reg_desc *found_reg(const char *name, enum reg_type *type)
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{
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unsigned int i, j;
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const struct reg_desc *desc;
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for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
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desc = ddr_registers[i].desc;
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for (j = 0; j < ddr_registers[i].size; j++) {
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if (strcmp(name, desc[j].name) == 0) {
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*type = i;
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return &desc[j];
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}
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}
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}
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*type = REG_TYPE_NB;
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return NULL;
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}
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int stm32mp1_dump_reg(const struct ddr_info *priv,
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const char *name)
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{
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unsigned int i, j;
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const struct reg_desc *desc;
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u32 base_addr;
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enum base_type p_base;
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enum reg_type type;
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const char *p_name;
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enum base_type filter = NONE_BASE;
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int result = -1;
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if (name) {
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if (strcmp(name, base_name[DDR_BASE]) == 0)
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filter = DDR_BASE;
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else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
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filter = DDRPHY_BASE;
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}
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for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
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p_base = ddr_registers[i].base;
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p_name = ddr_registers[i].name;
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if (!name || (filter == p_base || !strcmp(name, p_name))) {
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result = 0;
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desc = ddr_registers[i].desc;
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base_addr = get_base_addr(priv, p_base);
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printf("==%s.%s==\n", base_name[p_base], p_name);
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for (j = 0; j < ddr_registers[i].size; j++)
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stm32mp1_dump_reg_desc(base_addr, &desc[j]);
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}
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}
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if (result) {
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desc = found_reg(name, &type);
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if (desc) {
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p_base = ddr_registers[type].base;
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base_addr = get_base_addr(priv, p_base);
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stm32mp1_dump_reg_desc(base_addr, desc);
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result = 0;
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}
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}
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return result;
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}
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void stm32mp1_edit_reg(const struct ddr_info *priv,
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char *name, char *string)
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{
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unsigned long *ptr, value;
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enum reg_type type;
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enum base_type base;
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const struct reg_desc *desc;
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u32 base_addr;
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desc = found_reg(name, &type);
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if (!desc) {
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printf("%s not found\n", name);
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return;
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}
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if (strict_strtoul(string, 16, &value) < 0) {
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printf("invalid value %s\n", string);
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return;
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}
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base = ddr_registers[type].base;
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base_addr = get_base_addr(priv, base);
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ptr = (unsigned long *)(base_addr + desc->offset);
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writel(value, ptr);
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printf("%s= 0x%08x\n", desc->name, readl(ptr));
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}
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static u32 get_par_addr(const struct stm32mp1_ddr_config *config,
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enum reg_type type)
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{
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u32 par_addr = 0x0;
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switch (type) {
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case REG_REG:
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par_addr = (u32)&config->c_reg;
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break;
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case REG_TIMING:
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par_addr = (u32)&config->c_timing;
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break;
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case REG_PERF:
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par_addr = (u32)&config->c_perf;
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break;
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case REG_MAP:
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par_addr = (u32)&config->c_map;
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break;
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case REGPHY_REG:
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par_addr = (u32)&config->p_reg;
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break;
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case REGPHY_TIMING:
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par_addr = (u32)&config->p_timing;
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break;
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case REGPHY_CAL:
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par_addr = (u32)&config->p_cal;
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break;
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case REG_DYN:
|
|
case REGPHY_DYN:
|
|
case REG_TYPE_NB:
|
|
par_addr = (u32)NULL;
|
|
break;
|
|
}
|
|
|
|
return par_addr;
|
|
}
|
|
|
|
int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
|
|
const char *name)
|
|
{
|
|
unsigned int i, j;
|
|
const struct reg_desc *desc;
|
|
u32 par_addr;
|
|
enum base_type p_base;
|
|
enum reg_type type;
|
|
const char *p_name;
|
|
enum base_type filter = NONE_BASE;
|
|
int result = -EINVAL;
|
|
|
|
if (name) {
|
|
if (strcmp(name, base_name[DDR_BASE]) == 0)
|
|
filter = DDR_BASE;
|
|
else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
|
|
filter = DDRPHY_BASE;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
|
|
par_addr = get_par_addr(config, i);
|
|
if (!par_addr)
|
|
continue;
|
|
p_base = ddr_registers[i].base;
|
|
p_name = ddr_registers[i].name;
|
|
if (!name || (filter == p_base || !strcmp(name, p_name))) {
|
|
result = 0;
|
|
desc = ddr_registers[i].desc;
|
|
printf("==%s.%s==\n", base_name[p_base], p_name);
|
|
for (j = 0; j < ddr_registers[i].size; j++)
|
|
stm32mp1_dump_param_desc(par_addr, &desc[j]);
|
|
}
|
|
}
|
|
if (result) {
|
|
desc = found_reg(name, &type);
|
|
if (desc) {
|
|
par_addr = get_par_addr(config, type);
|
|
if (par_addr) {
|
|
stm32mp1_dump_param_desc(par_addr, desc);
|
|
result = 0;
|
|
}
|
|
}
|
|
}
|
|
return result;
|
|
}
|
|
|
|
void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
|
|
char *name, char *string)
|
|
{
|
|
unsigned long *ptr, value;
|
|
enum reg_type type;
|
|
const struct reg_desc *desc;
|
|
u32 par_addr;
|
|
|
|
desc = found_reg(name, &type);
|
|
if (!desc) {
|
|
printf("%s not found\n", name);
|
|
return;
|
|
}
|
|
if (strict_strtoul(string, 16, &value) < 0) {
|
|
printf("invalid value %s\n", string);
|
|
return;
|
|
}
|
|
par_addr = get_par_addr(config, type);
|
|
if (!par_addr) {
|
|
printf("no parameter %s\n", name);
|
|
return;
|
|
}
|
|
ptr = (unsigned long *)(par_addr + desc->par_offset);
|
|
writel(value, ptr);
|
|
printf("%s= 0x%08x\n", desc->name, readl(ptr));
|
|
}
|
|
#endif
|
|
|
|
__weak bool stm32mp1_ddr_interactive(void *priv,
|
|
enum stm32mp1_ddr_interact_step step,
|
|
const struct stm32mp1_ddr_config *config)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
#define INTERACTIVE(step)\
|
|
stm32mp1_ddr_interactive(priv, step, config)
|
|
|
|
static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
|
|
{
|
|
u32 pgsr;
|
|
int ret;
|
|
|
|
ret = readl_poll_timeout(&phy->pgsr, pgsr,
|
|
pgsr & (DDRPHYC_PGSR_IDONE |
|
|
DDRPHYC_PGSR_DTERR |
|
|
DDRPHYC_PGSR_DTIERR |
|
|
DDRPHYC_PGSR_DFTERR |
|
|
DDRPHYC_PGSR_RVERR |
|
|
DDRPHYC_PGSR_RVEIRR),
|
|
1000000);
|
|
debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
|
|
(u32)&phy->pgsr, pgsr, ret);
|
|
}
|
|
|
|
void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
|
|
{
|
|
pir |= DDRPHYC_PIR_INIT;
|
|
writel(pir, &phy->pir);
|
|
debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
|
|
(u32)&phy->pir, pir, readl(&phy->pir));
|
|
|
|
/* need to wait 10 configuration clock before start polling */
|
|
udelay(10);
|
|
|
|
/* Wait DRAM initialization and Gate Training Evaluation complete */
|
|
ddrphy_idone_wait(phy);
|
|
}
|
|
|
|
/* start quasi dynamic register update */
|
|
static void start_sw_done(struct stm32mp1_ddrctl *ctl)
|
|
{
|
|
clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
|
|
}
|
|
|
|
/* wait quasi dynamic register update */
|
|
static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
|
|
{
|
|
int ret;
|
|
u32 swstat;
|
|
|
|
setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
|
|
|
|
ret = readl_poll_timeout(&ctl->swstat, swstat,
|
|
swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
|
|
1000000);
|
|
if (ret)
|
|
panic("Timeout initialising DRAM : DDR->swstat = %x\n",
|
|
swstat);
|
|
|
|
debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
|
|
}
|
|
|
|
/* wait quasi dynamic register update */
|
|
static void wait_operating_mode(struct ddr_info *priv, int mode)
|
|
{
|
|
u32 stat, val, mask, val2 = 0, mask2 = 0;
|
|
int ret;
|
|
|
|
mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
|
|
val = mode;
|
|
/* self-refresh due to software => check also STAT.selfref_type */
|
|
if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
|
|
mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
|
|
val |= DDRCTRL_STAT_SELFREF_TYPE_SR;
|
|
} else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
|
|
/* normal mode: handle also automatic self refresh */
|
|
mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
|
|
DDRCTRL_STAT_SELFREF_TYPE_MASK;
|
|
val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
|
|
DDRCTRL_STAT_SELFREF_TYPE_ASR;
|
|
}
|
|
|
|
ret = readl_poll_timeout(&priv->ctl->stat, stat,
|
|
((stat & mask) == val) ||
|
|
(mask2 && ((stat & mask2) == val2)),
|
|
1000000);
|
|
|
|
if (ret)
|
|
panic("Timeout DRAM : DDR->stat = %x\n", stat);
|
|
|
|
debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
|
|
}
|
|
|
|
void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
|
|
{
|
|
start_sw_done(ctl);
|
|
/* quasi-dynamic register update*/
|
|
setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
|
|
clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN |
|
|
DDRCTRL_PWRCTL_SELFREF_EN);
|
|
clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
|
wait_sw_done_ack(ctl);
|
|
}
|
|
|
|
void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
|
|
u32 rfshctl3, u32 pwrctl)
|
|
{
|
|
start_sw_done(ctl);
|
|
if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
|
|
clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
|
|
if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
|
|
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
|
|
if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN))
|
|
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
|
|
setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
|
wait_sw_done_ack(ctl);
|
|
}
|
|
|
|
/* board-specific DDR power initializations. */
|
|
__weak int board_ddr_power_init(enum ddr_type ddr_type)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
__maybe_unused
|
|
void stm32mp1_ddr_init(struct ddr_info *priv,
|
|
const struct stm32mp1_ddr_config *config)
|
|
{
|
|
u32 pir;
|
|
int ret = -EINVAL;
|
|
char bus_width;
|
|
|
|
switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
|
|
case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
|
|
bus_width = 8;
|
|
break;
|
|
case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
|
|
bus_width = 16;
|
|
break;
|
|
default:
|
|
bus_width = 32;
|
|
break;
|
|
}
|
|
|
|
|
|
if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
|
|
ret = board_ddr_power_init(STM32MP_DDR3);
|
|
else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) {
|
|
if (bus_width == 32)
|
|
ret = board_ddr_power_init(STM32MP_LPDDR2_32);
|
|
else
|
|
ret = board_ddr_power_init(STM32MP_LPDDR2_16);
|
|
} else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) {
|
|
if (bus_width == 32)
|
|
ret = board_ddr_power_init(STM32MP_LPDDR3_32);
|
|
else
|
|
ret = board_ddr_power_init(STM32MP_LPDDR3_16);
|
|
}
|
|
if (ret)
|
|
panic("ddr power init failed\n");
|
|
|
|
start:
|
|
debug("name = %s\n", config->info.name);
|
|
debug("speed = %d kHz\n", config->info.speed);
|
|
debug("size = 0x%x\n", config->info.size);
|
|
/*
|
|
* 1. Program the DWC_ddr_umctl2 registers
|
|
* 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
|
|
*/
|
|
/* Assert All DDR part */
|
|
setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
|
|
setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
|
|
setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
|
|
setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
|
|
setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
|
|
setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
|
|
|
|
/* 1.2. start CLOCK */
|
|
if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
|
|
panic("invalid DRAM clock : %d kHz\n",
|
|
config->info.speed);
|
|
|
|
/* 1.3. deassert reset */
|
|
/* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
|
|
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
|
|
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
|
|
/* De-assert presetn once the clocks are active
|
|
* and stable via DDRCAPBRST bit
|
|
*/
|
|
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
|
|
|
|
/* 1.4. wait 128 cycles to permit initialization of end logic */
|
|
udelay(2);
|
|
/* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
|
|
|
|
if (INTERACTIVE(STEP_DDR_RESET))
|
|
goto start;
|
|
|
|
/* 1.5. initialize registers ddr_umctl2 */
|
|
/* Stop uMCTL2 before PHY is ready */
|
|
clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
|
debug("[0x%08x] dfimisc = 0x%08x\n",
|
|
(u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
|
|
|
|
set_reg(priv, REG_REG, &config->c_reg);
|
|
set_reg(priv, REG_TIMING, &config->c_timing);
|
|
set_reg(priv, REG_MAP, &config->c_map);
|
|
|
|
/* skip CTRL init, SDRAM init is done by PHY PUBL */
|
|
clrsetbits_le32(&priv->ctl->init0,
|
|
DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
|
|
DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
|
|
|
|
set_reg(priv, REG_PERF, &config->c_perf);
|
|
|
|
if (INTERACTIVE(STEP_CTL_INIT))
|
|
goto start;
|
|
|
|
/* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
|
|
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
|
|
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
|
|
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
|
|
|
|
/* 3. start PHY init by accessing relevant PUBL registers
|
|
* (DXGCR, DCR, PTR*, MR*, DTPR*)
|
|
*/
|
|
set_reg(priv, REGPHY_REG, &config->p_reg);
|
|
set_reg(priv, REGPHY_TIMING, &config->p_timing);
|
|
if (config->p_cal_present)
|
|
set_reg(priv, REGPHY_CAL, &config->p_cal);
|
|
|
|
if (INTERACTIVE(STEP_PHY_INIT))
|
|
goto start;
|
|
|
|
/* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE
|
|
* Perform DDR PHY DRAM initialization and Gate Training Evaluation
|
|
*/
|
|
ddrphy_idone_wait(priv->phy);
|
|
|
|
/* 5. Indicate to PUBL that controller performs SDRAM initialization
|
|
* by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
|
|
* DRAM init is done by PHY, init0.skip_dram.init = 1
|
|
*/
|
|
pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
|
|
DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
|
|
|
|
if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
|
|
pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
|
|
|
|
stm32mp1_ddrphy_init(priv->phy, pir);
|
|
|
|
/* 6. SET DFIMISC.dfi_init_complete_en to 1 */
|
|
/* Enable quasi-dynamic register programming*/
|
|
start_sw_done(priv->ctl);
|
|
setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
|
|
wait_sw_done_ack(priv->ctl);
|
|
|
|
/* 7. Wait for DWC_ddr_umctl2 to move to normal operation mode
|
|
* by monitoring STAT.operating_mode signal
|
|
*/
|
|
/* wait uMCTL2 ready */
|
|
|
|
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
|
|
|
|
if (config->p_cal_present) {
|
|
debug("DDR DQS training skipped.\n");
|
|
} else {
|
|
debug("DDR DQS training : ");
|
|
/* 8. Disable Auto refresh and power down by setting
|
|
* - RFSHCTL3.dis_au_refresh = 1
|
|
* - PWRCTL.powerdown_en = 0
|
|
* - DFIMISC.dfiinit_complete_en = 0
|
|
*/
|
|
stm32mp1_refresh_disable(priv->ctl);
|
|
|
|
/* 9. Program PUBL PGCR to enable refresh during training and rank to train
|
|
* not done => keep the programed value in PGCR
|
|
*/
|
|
|
|
/* 10. configure PUBL PIR register to specify which training step to run */
|
|
/* warning : RVTRN is not supported by this PUBL */
|
|
stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
|
|
|
|
/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
|
|
ddrphy_idone_wait(priv->phy);
|
|
|
|
/* 12. set back registers in step 8 to the orginal values if desidered */
|
|
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
|
|
config->c_reg.pwrctl);
|
|
} /* if (config->p_cal_present) */
|
|
|
|
/* enable uMCTL2 AXI port 0 and 1 */
|
|
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
|
|
setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
|
|
|
|
if (INTERACTIVE(STEP_DDR_READY))
|
|
goto start;
|
|
}
|