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https://github.com/brain-hackers/u-boot-brain
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8dfc15f56c
This patch in general spit SoC type clock dependent code and general clock code. Before adding keystone II Edison k2e SoC which has slightly different dpll set, move k2hk dependent clock code to separate clock-k2hk.c file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
89 lines
1.9 KiB
C
89 lines
1.9 KiB
C
/*
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* K2HK: Clock management APIs
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_K2HK_H
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#define __ASM_ARCH_CLOCK_K2HK_H
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enum ext_clk_e {
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sys_clk,
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alt_core_clk,
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pa_clk,
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tetris_clk,
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ddr3a_clk,
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ddr3b_clk,
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mcm_clk,
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pcie_clk,
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sgmii_srio_clk,
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xgmii_clk,
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usb_clk,
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rp1_clk,
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ext_clk_count /* number of external clocks */
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};
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extern unsigned int external_clk[ext_clk_count];
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enum clk_e {
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core_pll_clk,
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pass_pll_clk,
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tetris_pll_clk,
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ddr3a_pll_clk,
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ddr3b_pll_clk,
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sys_clk0_clk,
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sys_clk0_1_clk,
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sys_clk0_2_clk,
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sys_clk0_3_clk,
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sys_clk0_4_clk,
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sys_clk0_6_clk,
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sys_clk0_8_clk,
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sys_clk0_12_clk,
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sys_clk0_24_clk,
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sys_clk1_clk,
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sys_clk1_3_clk,
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sys_clk1_4_clk,
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sys_clk1_6_clk,
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sys_clk1_12_clk,
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sys_clk2_clk,
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sys_clk3_clk
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};
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#define KS2_CLK1_6 sys_clk0_6_clk
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/* PLL identifiers */
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enum pll_type_e {
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CORE_PLL,
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PASS_PLL,
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TETRIS_PLL,
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DDR3A_PLL,
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DDR3B_PLL,
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};
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#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
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#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
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#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
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#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
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#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
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#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
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#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
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#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
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#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
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#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
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#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
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#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
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#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
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#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
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#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
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#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
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#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
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#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
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#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
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#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
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#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
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#endif
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