mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
d6a61da462
Remove ad-hoc ethernet syscon registers configuration and reset support. Reset is now handled by the reset framework and the syscon registers are set in the dwmac_socfpga.c driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#include <altera.h>
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <ns16550.h>
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#include <watchdog.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/reset_manager_arria10.h>
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#include <asm/arch/sdram_arria10.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/nic301.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
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#if defined(CONFIG_SPL_BUILD)
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
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(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
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#endif
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static struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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#if defined(CONFIG_SPL_BUILD)
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/*
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+ * This function initializes security policies to be consistent across
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+ * all logic units in the Arria 10.
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+ *
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+ * The idea is to set all security policies to be normal, nonsecure
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+ * for all units.
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+ */
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static void initialize_security_policies(void)
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{
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/* Put OCRAM in non-secure */
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writel(0x003f0000, &noc_fw_ocram_base->region0);
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writel(0x1, &noc_fw_ocram_base->enable);
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/* Put DDR in non-secure */
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writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc);
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writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS);
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/* Enable priviledged and non-priviledged access to L4 peripherals */
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writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST);
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/* Enable secure and non-secure transactions to bridges */
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writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
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writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
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writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
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}
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int arch_early_init_r(void)
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{
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initialize_security_policies();
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/* Configure the L2 controller to make SDRAM start at 0 */
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writel(0x1, &pl310->pl310_addr_filter_start);
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/* assert reset to all except L4WD0 and L4TIMER0 */
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socfpga_per_reset_all();
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return 0;
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}
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#else
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int arch_early_init_r(void)
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{
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return 0;
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}
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#endif
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/*
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* Print CPU information
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*/
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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const u32 bsel =
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SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
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puts("CPU: Altera SoCFPGA Arria 10\n");
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printf("BOOT: %s\n", bsel_str[bsel].name);
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return 0;
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}
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#endif
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void do_bridge_reset(int enable)
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{
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if (enable)
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socfpga_reset_deassert_bridges_handoff();
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else
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socfpga_bridges_reset();
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}
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