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![Sricharan](/assets/img/avatar_default.png)
Much of omap4 soc support code can be reused for omap5. Move them to the omap-common directory to facilitate this. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
942 lines
28 KiB
C
942 lines
28 KiB
C
/*
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*
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* Clock initialization for OMAP4
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*
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* Based on previous work by:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Rajendra Nayak <rnayak@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/omap_common.h>
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#include <asm/gpio.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/utils.h>
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#include <asm/omap_gpio.h>
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#ifndef CONFIG_SPL_BUILD
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/*
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* printing to console doesn't work unless
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* this code is executed from SPL
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*/
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#define printf(fmt, args...)
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#define puts(s)
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#endif
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#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
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struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
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static const u32 sys_clk_array[8] = {
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12000000, /* 12 MHz */
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13000000, /* 13 MHz */
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16800000, /* 16.8 MHz */
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19200000, /* 19.2 MHz */
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26000000, /* 26 MHz */
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27000000, /* 27 MHz */
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38400000, /* 38.4 MHz */
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};
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/*
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* The M & N values in the following tables are created using the
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* following tool:
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* tools/omap/clocks_get_m_n.c
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* Please use this tool for creating the table for any new frequency.
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*/
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/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
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static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
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{230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
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static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
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{66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
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static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
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{50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
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{800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
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{619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
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{125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
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{400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
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{800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
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{125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
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};
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static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
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{127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
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{762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
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{635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
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{635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
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{381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
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{254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
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{496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
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};
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static const struct dpll_params
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core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
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{200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
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{800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
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{619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
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{125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
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{400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
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{800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
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{125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
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};
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static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
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{64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
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{768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
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{320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
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{40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
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{384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
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{256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
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{20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
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};
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static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
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{931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
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{931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
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{665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
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{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
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{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
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{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
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{412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with sys_clk as source */
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static const struct dpll_params
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abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
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{49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
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{68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
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{35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
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{46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
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{34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
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{29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
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{64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with 32K clock as source */
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static const struct dpll_params abe_dpll_params_32k_196608khz = {
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750, 0, 1, 1, -1, -1, -1, -1
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};
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static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
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{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
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{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
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{400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
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{320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
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{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static inline u32 __get_sys_clk_index(void)
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{
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u32 ind;
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/*
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* For ES1 the ROM code calibration of sys clock is not reliable
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* due to hw issue. So, use hard-coded value. If this value is not
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* correct for any board over-ride this function in board file
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* From ES2.0 onwards you will get this information from
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* CM_SYS_CLKSEL
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*/
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if (omap_revision() == OMAP4430_ES1_0)
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ind = OMAP_SYS_CLK_IND_38_4_MHZ;
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else {
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/* SYS_CLKSEL - 1 to match the dpll param array indices */
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ind = (readl(&prcm->cm_sys_clksel) &
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CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
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}
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return ind;
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}
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u32 get_sys_clk_index(void)
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__attribute__ ((weak, alias("__get_sys_clk_index")));
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u32 get_sys_clk_freq(void)
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{
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u8 index = get_sys_clk_index();
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return sys_clk_array[index];
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}
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static inline void do_bypass_dpll(u32 *const base)
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{
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struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
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clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_FAST_RELOCK_BYPASS <<
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CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_bypass(u32 *const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
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LDELAY)) {
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printf("Bypassing DPLL failed %p\n", base);
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}
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}
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static inline void do_lock_dpll(u32 *const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_lock(u32 *const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
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&dpll_regs->cm_idlest_dpll, LDELAY)) {
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printf("DPLL locking failed for %p\n", base);
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hang();
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}
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}
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static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
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u8 lock)
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{
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u32 temp;
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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bypass_dpll(base);
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/* Set M & N */
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temp = readl(&dpll_regs->cm_clksel_dpll);
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temp &= ~CM_CLKSEL_DPLL_M_MASK;
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temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
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temp &= ~CM_CLKSEL_DPLL_N_MASK;
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temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
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writel(temp, &dpll_regs->cm_clksel_dpll);
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/* Lock */
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if (lock)
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do_lock_dpll(base);
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/* Setup post-dividers */
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if (params->m2 >= 0)
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writel(params->m2, &dpll_regs->cm_div_m2_dpll);
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if (params->m3 >= 0)
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writel(params->m3, &dpll_regs->cm_div_m3_dpll);
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if (params->m4 >= 0)
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writel(params->m4, &dpll_regs->cm_div_m4_dpll);
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if (params->m5 >= 0)
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writel(params->m5, &dpll_regs->cm_div_m5_dpll);
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if (params->m6 >= 0)
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writel(params->m6, &dpll_regs->cm_div_m6_dpll);
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if (params->m7 >= 0)
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writel(params->m7, &dpll_regs->cm_div_m7_dpll);
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/* Wait till the DPLL locks */
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if (lock)
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wait_for_lock(base);
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}
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const struct dpll_params *get_core_dpll_params(void)
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{
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u32 sysclk_ind = get_sys_clk_index();
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switch (omap_revision()) {
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case OMAP4430_ES1_0:
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return &core_dpll_params_es1_1524mhz[sysclk_ind];
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case OMAP4430_ES2_0:
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case OMAP4430_SILICON_ID_INVALID:
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/* safest */
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return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
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default:
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return &core_dpll_params_1600mhz[sysclk_ind];
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}
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}
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u32 omap4_ddr_clk(void)
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{
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u32 ddr_clk, sys_clk_khz;
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const struct dpll_params *core_dpll_params;
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sys_clk_khz = get_sys_clk_freq() / 1000;
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core_dpll_params = get_core_dpll_params();
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debug("sys_clk %d\n ", sys_clk_khz * 1000);
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/* Find Core DPLL locked frequency first */
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ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
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(core_dpll_params->n + 1);
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/*
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* DDR frequency is PHY_ROOT_CLK/2
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* PHY_ROOT_CLK = Fdpll/2/M2
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*/
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ddr_clk = ddr_clk / 4 / core_dpll_params->m2;
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ddr_clk *= 1000; /* convert to Hz */
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debug("ddr_clk %d\n ", ddr_clk);
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return ddr_clk;
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}
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/*
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* Lock MPU dpll
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*
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* Resulting MPU frequencies:
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* 4430 ES1.0 : 600 MHz
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* 4430 ES2.x : 792 MHz (OPP Turbo)
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* 4460 : 920 MHz (OPP Turbo) - DCC disabled
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*/
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void configure_mpu_dpll(void)
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{
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const struct dpll_params *params;
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struct dpll_regs *mpu_dpll_regs;
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u32 omap4_rev, sysclk_ind;
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omap4_rev = omap_revision();
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sysclk_ind = get_sys_clk_index();
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if (omap4_rev == OMAP4430_ES1_0)
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params = &mpu_dpll_params_1200mhz[sysclk_ind];
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else if (omap4_rev < OMAP4460_ES1_0)
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params = &mpu_dpll_params_1584mhz[sysclk_ind];
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else
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params = &mpu_dpll_params_1840mhz[sysclk_ind];
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/* DCC and clock divider settings for 4460 */
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if (omap4_rev >= OMAP4460_ES1_0) {
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mpu_dpll_regs =
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(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
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bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
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clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
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setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
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clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
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CM_CLKSEL_DCC_EN_MASK);
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}
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do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
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debug("MPU DPLL locked\n");
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}
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static void setup_dplls(void)
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{
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u32 sysclk_ind, temp;
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const struct dpll_params *params;
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debug("setup_dplls\n");
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sysclk_ind = get_sys_clk_index();
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/* CORE dpll */
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params = get_core_dpll_params(); /* default - safest */
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/*
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* Do not lock the core DPLL now. Just set it up.
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* Core DPLL will be locked after setting up EMIF
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* using the FREQ_UPDATE method(freq_update_core())
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*/
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do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
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/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
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temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
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(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
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(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
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writel(temp, &prcm->cm_clksel_core);
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debug("Core DPLL configured\n");
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/* lock PER dpll */
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|
do_setup_dpll(&prcm->cm_clkmode_dpll_per,
|
|
&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK);
|
|
debug("PER DPLL locked\n");
|
|
|
|
/* MPU dpll */
|
|
configure_mpu_dpll();
|
|
}
|
|
|
|
static void setup_non_essential_dplls(void)
|
|
{
|
|
u32 sys_clk_khz, abe_ref_clk;
|
|
u32 sysclk_ind, sd_div, num, den;
|
|
const struct dpll_params *params;
|
|
|
|
sysclk_ind = get_sys_clk_index();
|
|
sys_clk_khz = get_sys_clk_freq() / 1000;
|
|
|
|
/* IVA */
|
|
clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
|
|
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
|
|
|
|
do_setup_dpll(&prcm->cm_clkmode_dpll_iva,
|
|
&iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK);
|
|
|
|
/*
|
|
* USB:
|
|
* USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
|
|
* DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
|
|
* - where CLKINP is sys_clk in MHz
|
|
* Use CLKINP in KHz and adjust the denominator accordingly so
|
|
* that we have enough accuracy and at the same time no overflow
|
|
*/
|
|
params = &usb_dpll_params_1920mhz[sysclk_ind];
|
|
num = params->m * sys_clk_khz;
|
|
den = (params->n + 1) * 250 * 1000;
|
|
num += den - 1;
|
|
sd_div = num / den;
|
|
clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
|
|
CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
|
|
sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
|
|
|
|
/* Now setup the dpll with the regular function */
|
|
do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
|
|
|
|
#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK
|
|
params = &abe_dpll_params_sysclk_196608khz[sysclk_ind];
|
|
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
|
|
#else
|
|
params = &abe_dpll_params_32k_196608khz;
|
|
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
|
|
/*
|
|
* We need to enable some additional options to achieve
|
|
* 196.608MHz from 32768 Hz
|
|
*/
|
|
setbits_le32(&prcm->cm_clkmode_dpll_abe,
|
|
CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
|
|
CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
|
|
CM_CLKMODE_DPLL_LPMODE_EN_MASK|
|
|
CM_CLKMODE_DPLL_REGM4XEN_MASK);
|
|
/* Spend 4 REFCLK cycles at each stage */
|
|
clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
|
|
CM_CLKMODE_DPLL_RAMP_RATE_MASK,
|
|
1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
|
|
#endif
|
|
|
|
/* Select the right reference clk */
|
|
clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
|
|
CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
|
|
abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
|
|
/* Lock the dpll */
|
|
do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
|
|
}
|
|
|
|
static void do_scale_tps62361(u32 reg, u32 volt_mv)
|
|
{
|
|
u32 temp, step;
|
|
|
|
step = volt_mv - TPS62361_BASE_VOLT_MV;
|
|
step /= 10;
|
|
|
|
/*
|
|
* Select SET1 in TPS62361:
|
|
* VSEL1 is grounded on board. So the following selects
|
|
* VSEL1 = 0 and VSEL0 = 1
|
|
*/
|
|
gpio_direction_output(TPS62361_VSEL0_GPIO, 0);
|
|
gpio_set_value(TPS62361_VSEL0_GPIO, 1);
|
|
|
|
temp = TPS62361_I2C_SLAVE_ADDR |
|
|
(reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
|
|
(step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
|
|
PRM_VC_VAL_BYPASS_VALID_BIT;
|
|
debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
|
|
|
|
writel(temp, &prcm->prm_vc_val_bypass);
|
|
if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
|
|
&prcm->prm_vc_val_bypass, LDELAY)) {
|
|
puts("Scaling voltage failed for vdd_mpu from TPS\n");
|
|
}
|
|
}
|
|
|
|
static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
|
|
{
|
|
u32 temp, offset_code;
|
|
u32 step = 12660; /* 12.66 mV represented in uV */
|
|
u32 offset = volt_mv;
|
|
|
|
/* convert to uV for better accuracy in the calculations */
|
|
offset *= 1000;
|
|
|
|
if (omap_revision() == OMAP4430_ES1_0)
|
|
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
|
|
else
|
|
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
|
|
|
|
offset_code = (offset + step - 1) / step;
|
|
/* The code starts at 1 not 0 */
|
|
offset_code++;
|
|
|
|
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
|
|
offset_code);
|
|
|
|
temp = SMPS_I2C_SLAVE_ADDR |
|
|
(vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
|
|
(offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
|
|
PRM_VC_VAL_BYPASS_VALID_BIT;
|
|
writel(temp, &prcm->prm_vc_val_bypass);
|
|
if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
|
|
&prcm->prm_vc_val_bypass, LDELAY)) {
|
|
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
|
|
* We set the maximum voltages allowed here because Smart-Reflex is not
|
|
* enabled in bootloader. Voltage initialization in the kernel will set
|
|
* these to the nominal values after enabling Smart-Reflex
|
|
*/
|
|
static void scale_vcores(void)
|
|
{
|
|
u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev;
|
|
|
|
sys_clk_khz = get_sys_clk_freq() / 1000;
|
|
|
|
/*
|
|
* Setup the dedicated I2C controller for Voltage Control
|
|
* I2C clk - high period 40% low period 60%
|
|
*/
|
|
cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
|
|
cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
|
|
/* values to be set in register - less by 5 & 7 respectively */
|
|
cycles_hi -= 5;
|
|
cycles_low -= 7;
|
|
temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
|
|
(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
|
|
writel(temp, &prcm->prm_vc_cfg_i2c_clk);
|
|
|
|
/* Disable high speed mode and all advanced features */
|
|
writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
|
|
|
|
omap4_rev = omap_revision();
|
|
/* TPS - supplies vdd_mpu on 4460 */
|
|
if (omap4_rev >= OMAP4460_ES1_0) {
|
|
volt = 1430;
|
|
do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
|
|
}
|
|
|
|
/*
|
|
* VCORE 1
|
|
*
|
|
* 4430 : supplies vdd_mpu
|
|
* Setting a high voltage for Nitro mode as smart reflex is not enabled.
|
|
* We use the maximum possible value in the AVS range because the next
|
|
* higher voltage in the discrete range (code >= 0b111010) is way too
|
|
* high
|
|
*
|
|
* 4460 : supplies vdd_core
|
|
*/
|
|
if (omap4_rev < OMAP4460_ES1_0) {
|
|
volt = 1417;
|
|
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
|
|
} else {
|
|
volt = 1200;
|
|
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
|
|
}
|
|
|
|
/* VCORE 2 - supplies vdd_iva */
|
|
volt = 1200;
|
|
do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
|
|
|
|
/*
|
|
* VCORE 3
|
|
* 4430 : supplies vdd_core
|
|
* 4460 : not connected
|
|
*/
|
|
if (omap4_rev < OMAP4460_ES1_0) {
|
|
volt = 1200;
|
|
do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
|
|
}
|
|
}
|
|
|
|
static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
|
|
{
|
|
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
|
|
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
|
|
debug("Enable clock domain - %p\n", clkctrl_reg);
|
|
}
|
|
|
|
static inline void wait_for_clk_enable(u32 *clkctrl_addr)
|
|
{
|
|
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
|
|
u32 bound = LDELAY;
|
|
|
|
while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
|
|
(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
|
|
|
|
clkctrl = readl(clkctrl_addr);
|
|
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
|
|
MODULE_CLKCTRL_IDLEST_SHIFT;
|
|
if (--bound == 0) {
|
|
printf("Clock enable failed for 0x%p idlest 0x%x\n",
|
|
clkctrl_addr, clkctrl);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
|
|
u32 wait_for_enable)
|
|
{
|
|
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
debug("Enable clock module - %p\n", clkctrl_addr);
|
|
if (wait_for_enable)
|
|
wait_for_clk_enable(clkctrl_addr);
|
|
}
|
|
|
|
/*
|
|
* Enable essential clock domains, modules and
|
|
* do some additional special settings needed
|
|
*/
|
|
static void enable_basic_clocks(void)
|
|
{
|
|
u32 i, max = 100, wait_for_enable = 1;
|
|
u32 *const clk_domains_essential[] = {
|
|
&prcm->cm_l4per_clkstctrl,
|
|
&prcm->cm_l3init_clkstctrl,
|
|
&prcm->cm_memif_clkstctrl,
|
|
&prcm->cm_l4cfg_clkstctrl,
|
|
0
|
|
};
|
|
|
|
u32 *const clk_modules_hw_auto_essential[] = {
|
|
&prcm->cm_wkup_gpio1_clkctrl,
|
|
&prcm->cm_l4per_gpio2_clkctrl,
|
|
&prcm->cm_l4per_gpio3_clkctrl,
|
|
&prcm->cm_l4per_gpio4_clkctrl,
|
|
&prcm->cm_l4per_gpio5_clkctrl,
|
|
&prcm->cm_l4per_gpio6_clkctrl,
|
|
&prcm->cm_memif_emif_1_clkctrl,
|
|
&prcm->cm_memif_emif_2_clkctrl,
|
|
&prcm->cm_l3init_hsusbotg_clkctrl,
|
|
&prcm->cm_l3init_usbphy_clkctrl,
|
|
&prcm->cm_l4cfg_l4_cfg_clkctrl,
|
|
0
|
|
};
|
|
|
|
u32 *const clk_modules_explicit_en_essential[] = {
|
|
&prcm->cm_l4per_gptimer2_clkctrl,
|
|
&prcm->cm_l3init_hsmmc1_clkctrl,
|
|
&prcm->cm_l3init_hsmmc2_clkctrl,
|
|
&prcm->cm_l4per_mcspi1_clkctrl,
|
|
&prcm->cm_wkup_gptimer1_clkctrl,
|
|
&prcm->cm_l4per_i2c1_clkctrl,
|
|
&prcm->cm_l4per_i2c2_clkctrl,
|
|
&prcm->cm_l4per_i2c3_clkctrl,
|
|
&prcm->cm_l4per_i2c4_clkctrl,
|
|
&prcm->cm_wkup_wdtimer2_clkctrl,
|
|
&prcm->cm_l4per_uart3_clkctrl,
|
|
0
|
|
};
|
|
|
|
/* Enable optional additional functional clock for GPIO4 */
|
|
setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
|
|
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
|
|
|
|
/* Enable 96 MHz clock for MMC1 & MMC2 */
|
|
setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
|
|
HSMMC_CLKCTRL_CLKSEL_MASK);
|
|
setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
|
|
HSMMC_CLKCTRL_CLKSEL_MASK);
|
|
|
|
/* Select 32KHz clock as the source of GPTIMER1 */
|
|
setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
|
|
GPTIMER1_CLKCTRL_CLKSEL_MASK);
|
|
|
|
/* Enable optional 48M functional clock for USB PHY */
|
|
setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
|
|
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
|
|
|
|
/* Put the clock domains in SW_WKUP mode */
|
|
for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
|
|
enable_clock_domain(clk_domains_essential[i],
|
|
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
|
|
}
|
|
|
|
/* Clock modules that need to be put in HW_AUTO */
|
|
for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) {
|
|
enable_clock_module(clk_modules_hw_auto_essential[i],
|
|
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
|
|
wait_for_enable);
|
|
};
|
|
|
|
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
|
|
for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) {
|
|
enable_clock_module(clk_modules_explicit_en_essential[i],
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
|
|
wait_for_enable);
|
|
};
|
|
|
|
/* Put the clock domains in HW_AUTO mode now */
|
|
for (i = 0; (i < max) && clk_domains_essential[i]; i++) {
|
|
enable_clock_domain(clk_domains_essential[i],
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Enable non-essential clock domains, modules and
|
|
* do some additional special settings needed
|
|
*/
|
|
static void enable_non_essential_clocks(void)
|
|
{
|
|
u32 i, max = 100, wait_for_enable = 0;
|
|
u32 *const clk_domains_non_essential[] = {
|
|
&prcm->cm_mpu_m3_clkstctrl,
|
|
&prcm->cm_ivahd_clkstctrl,
|
|
&prcm->cm_dsp_clkstctrl,
|
|
&prcm->cm_dss_clkstctrl,
|
|
&prcm->cm_sgx_clkstctrl,
|
|
&prcm->cm1_abe_clkstctrl,
|
|
&prcm->cm_c2c_clkstctrl,
|
|
&prcm->cm_cam_clkstctrl,
|
|
&prcm->cm_dss_clkstctrl,
|
|
&prcm->cm_sdma_clkstctrl,
|
|
0
|
|
};
|
|
|
|
u32 *const clk_modules_hw_auto_non_essential[] = {
|
|
&prcm->cm_mpu_m3_mpu_m3_clkctrl,
|
|
&prcm->cm_ivahd_ivahd_clkctrl,
|
|
&prcm->cm_ivahd_sl2_clkctrl,
|
|
&prcm->cm_dsp_dsp_clkctrl,
|
|
&prcm->cm_l3_2_gpmc_clkctrl,
|
|
&prcm->cm_l3instr_l3_3_clkctrl,
|
|
&prcm->cm_l3instr_l3_instr_clkctrl,
|
|
&prcm->cm_l3instr_intrconn_wp1_clkctrl,
|
|
&prcm->cm_l3init_hsi_clkctrl,
|
|
&prcm->cm_l3init_hsusbtll_clkctrl,
|
|
0
|
|
};
|
|
|
|
u32 *const clk_modules_explicit_en_non_essential[] = {
|
|
&prcm->cm1_abe_aess_clkctrl,
|
|
&prcm->cm1_abe_pdm_clkctrl,
|
|
&prcm->cm1_abe_dmic_clkctrl,
|
|
&prcm->cm1_abe_mcasp_clkctrl,
|
|
&prcm->cm1_abe_mcbsp1_clkctrl,
|
|
&prcm->cm1_abe_mcbsp2_clkctrl,
|
|
&prcm->cm1_abe_mcbsp3_clkctrl,
|
|
&prcm->cm1_abe_slimbus_clkctrl,
|
|
&prcm->cm1_abe_timer5_clkctrl,
|
|
&prcm->cm1_abe_timer6_clkctrl,
|
|
&prcm->cm1_abe_timer7_clkctrl,
|
|
&prcm->cm1_abe_timer8_clkctrl,
|
|
&prcm->cm1_abe_wdt3_clkctrl,
|
|
&prcm->cm_l4per_gptimer9_clkctrl,
|
|
&prcm->cm_l4per_gptimer10_clkctrl,
|
|
&prcm->cm_l4per_gptimer11_clkctrl,
|
|
&prcm->cm_l4per_gptimer3_clkctrl,
|
|
&prcm->cm_l4per_gptimer4_clkctrl,
|
|
&prcm->cm_l4per_hdq1w_clkctrl,
|
|
&prcm->cm_l4per_mcbsp4_clkctrl,
|
|
&prcm->cm_l4per_mcspi2_clkctrl,
|
|
&prcm->cm_l4per_mcspi3_clkctrl,
|
|
&prcm->cm_l4per_mcspi4_clkctrl,
|
|
&prcm->cm_l4per_mmcsd3_clkctrl,
|
|
&prcm->cm_l4per_mmcsd4_clkctrl,
|
|
&prcm->cm_l4per_mmcsd5_clkctrl,
|
|
&prcm->cm_l4per_uart1_clkctrl,
|
|
&prcm->cm_l4per_uart2_clkctrl,
|
|
&prcm->cm_l4per_uart4_clkctrl,
|
|
&prcm->cm_wkup_keyboard_clkctrl,
|
|
&prcm->cm_wkup_wdtimer2_clkctrl,
|
|
&prcm->cm_cam_iss_clkctrl,
|
|
&prcm->cm_cam_fdif_clkctrl,
|
|
&prcm->cm_dss_dss_clkctrl,
|
|
&prcm->cm_sgx_sgx_clkctrl,
|
|
&prcm->cm_l3init_hsusbhost_clkctrl,
|
|
&prcm->cm_l3init_fsusb_clkctrl,
|
|
0
|
|
};
|
|
|
|
/* Enable optional functional clock for ISS */
|
|
setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
|
|
|
|
/* Enable all optional functional clocks of DSS */
|
|
setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
|
|
|
|
|
|
/* Put the clock domains in SW_WKUP mode */
|
|
for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
|
|
enable_clock_domain(clk_domains_non_essential[i],
|
|
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
|
|
}
|
|
|
|
/* Clock modules that need to be put in HW_AUTO */
|
|
for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) {
|
|
enable_clock_module(clk_modules_hw_auto_non_essential[i],
|
|
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
|
|
wait_for_enable);
|
|
};
|
|
|
|
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
|
|
for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i];
|
|
i++) {
|
|
enable_clock_module(clk_modules_explicit_en_non_essential[i],
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
|
|
wait_for_enable);
|
|
};
|
|
|
|
/* Put the clock domains in HW_AUTO mode now */
|
|
for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) {
|
|
enable_clock_domain(clk_domains_non_essential[i],
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
|
|
}
|
|
|
|
/* Put camera module in no sleep mode */
|
|
clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
}
|
|
|
|
|
|
void freq_update_core(void)
|
|
{
|
|
u32 freq_config1 = 0;
|
|
const struct dpll_params *core_dpll_params;
|
|
|
|
core_dpll_params = get_core_dpll_params();
|
|
/* Put EMIF clock domain in sw wakeup mode */
|
|
enable_clock_domain(&prcm->cm_memif_clkstctrl,
|
|
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
|
|
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
|
|
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
|
|
|
|
freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
|
|
SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
|
|
|
|
freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
|
|
SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
|
|
|
|
freq_config1 |= (core_dpll_params->m2 <<
|
|
SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
|
|
SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
|
|
|
|
writel(freq_config1, &prcm->cm_shadow_freq_config1);
|
|
if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
|
|
&prcm->cm_shadow_freq_config1, LDELAY)) {
|
|
puts("FREQ UPDATE procedure failed!!");
|
|
hang();
|
|
}
|
|
|
|
/* Put EMIF clock domain back in hw auto mode */
|
|
enable_clock_domain(&prcm->cm_memif_clkstctrl,
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
|
|
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
|
|
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
|
|
}
|
|
|
|
void bypass_dpll(u32 *const base)
|
|
{
|
|
do_bypass_dpll(base);
|
|
wait_for_bypass(base);
|
|
}
|
|
|
|
void lock_dpll(u32 *const base)
|
|
{
|
|
do_lock_dpll(base);
|
|
wait_for_lock(base);
|
|
}
|
|
|
|
void setup_clocks_for_console(void)
|
|
{
|
|
/* Do not add any spl_debug prints in this function */
|
|
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
|
|
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
|
|
CD_CLKCTRL_CLKTRCTRL_SHIFT);
|
|
|
|
/* Enable all UARTs - console will be on one of them */
|
|
clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
|
|
CD_CLKCTRL_CLKTRCTRL_SHIFT);
|
|
}
|
|
|
|
void prcm_init(void)
|
|
{
|
|
switch (omap4_hw_init_context()) {
|
|
case OMAP_INIT_CONTEXT_SPL:
|
|
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
|
|
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
|
|
enable_basic_clocks();
|
|
scale_vcores();
|
|
setup_dplls();
|
|
setup_non_essential_dplls();
|
|
enable_non_essential_clocks();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|