mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-10 20:23:54 +09:00
b90f0e7c37
No more use static frequency HSI = 64MHz for STGEN clock but HSE (with higher accurency) by default. Need to remove CONFIG_SYS_HZ_CLOCK as arch timer frequency is provided at boot by BootRom and cp15 cntfrq and modified during clock tree initialization if needed. When HSI is no more used by any device, this internal oscillator can be switched off to reduce consumption. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
156 lines
2.1 KiB
Plaintext
156 lines
2.1 KiB
Plaintext
/*
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* Copyright : STMicroelectronics 2018
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*
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* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
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*/
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp157-u-boot.dtsi"
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#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
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/ {
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aliases {
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mmc0 = &sdmmc1;
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mmc1 = &sdmmc2;
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i2c3 = &i2c4;
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};
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};
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&uart4_pins_a {
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u-boot,dm-pre-reloc;
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pins1 {
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u-boot,dm-pre-reloc;
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};
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pins2 {
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u-boot,dm-pre-reloc;
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};
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};
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&i2c4_pins_a {
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u-boot,dm-pre-reloc;
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pins {
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u-boot,dm-pre-reloc;
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};
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};
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&uart4 {
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u-boot,dm-pre-reloc;
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};
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&i2c4 {
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u-boot,dm-pre-reloc;
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};
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&pmic {
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u-boot,dm-pre-reloc;
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};
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/* CLOCK init */
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&rcc_clk {
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_DISABLED
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CLK_SDMMC12_PLL3R
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CLK_STGEN_HSE
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CLK_I2C46_PCLK5
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CLK_I2C12_PCLK1
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CLK_SDMMC3_PLL3R
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CLK_I2C35_PCLK1
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CLK_UART1_PCLK5
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CLK_UART24_PCLK1
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CLK_UART35_PCLK1
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CLK_UART6_PCLK2
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CLK_UART78_PCLK1
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>;
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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pll1: st,pll@0 {
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cfg = < 2 80 0 0 0 PQR(1,0,0) >;
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frac = < 0x800 >;
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u-boot,dm-pre-reloc;
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};
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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frac = < 0x1400 >;
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u-boot,dm-pre-reloc;
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};
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/* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
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pll3: st,pll@2 {
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cfg = < 3 128 3 20 7 PQR(1,1,1) >;
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u-boot,dm-pre-reloc;
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};
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/* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
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pll4: st,pll@3 {
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cfg = < 5 126 8 8 8 PQR(1,1,1) >;
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u-boot,dm-pre-reloc;
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};
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};
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/* SPL part **************************************/
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/* MMC1 boot */
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&sdmmc1_b4_pins_a {
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u-boot,dm-spl;
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pins {
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u-boot,dm-spl;
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};
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};
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&sdmmc1_dir_pins_a {
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u-boot,dm-spl;
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pins {
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u-boot,dm-spl;
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};
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};
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&sdmmc1 {
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u-boot,dm-spl;
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};
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/* MMC2 boot */
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&sdmmc2_b4_pins_a {
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u-boot,dm-spl;
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pins {
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u-boot,dm-spl;
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};
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};
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&sdmmc2_d47_pins_a {
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u-boot,dm-spl;
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pins {
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u-boot,dm-spl;
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};
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};
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&sdmmc2 {
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u-boot,dm-spl;
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};
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