86 lines
1.9 KiB
C
86 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Xilinx Zynq MPSoC Firmware driver
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*
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* Copyright (C) 2018-2019 Xilinx, Inc.
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*/
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#ifndef _ZYNQMP_FIRMWARE_H_
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#define _ZYNQMP_FIRMWARE_H_
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enum pm_api_id {
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PM_GET_API_VERSION = 1,
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PM_SET_CONFIGURATION,
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PM_GET_NODE_STATUS,
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PM_GET_OPERATING_CHARACTERISTIC,
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PM_REGISTER_NOTIFIER,
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PM_REQUEST_SUSPEND,
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PM_SELF_SUSPEND,
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PM_FORCE_POWERDOWN,
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PM_ABORT_SUSPEND,
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PM_REQUEST_WAKEUP,
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PM_SET_WAKEUP_SOURCE,
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PM_SYSTEM_SHUTDOWN,
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PM_REQUEST_NODE,
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PM_RELEASE_NODE,
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PM_SET_REQUIREMENT,
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PM_SET_MAX_LATENCY,
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PM_RESET_ASSERT,
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PM_RESET_GET_STATUS,
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PM_MMIO_WRITE,
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PM_MMIO_READ,
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PM_PM_INIT_FINALIZE,
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PM_FPGA_LOAD,
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PM_FPGA_GET_STATUS,
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PM_GET_CHIPID,
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PM_SECURE_SHA = 26,
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PM_SECURE_RSA,
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PM_PINCTRL_REQUEST,
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PM_PINCTRL_RELEASE,
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PM_PINCTRL_GET_FUNCTION,
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PM_PINCTRL_SET_FUNCTION,
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PM_PINCTRL_CONFIG_PARAM_GET,
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PM_PINCTRL_CONFIG_PARAM_SET,
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PM_IOCTL,
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PM_QUERY_DATA,
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PM_CLOCK_ENABLE,
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PM_CLOCK_DISABLE,
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PM_CLOCK_GETSTATE,
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PM_CLOCK_SETDIVIDER,
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PM_CLOCK_GETDIVIDER,
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PM_CLOCK_SETRATE,
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PM_CLOCK_GETRATE,
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PM_CLOCK_SETPARENT,
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PM_CLOCK_GETPARENT,
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PM_SECURE_IMAGE,
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PM_FPGA_READ = 46,
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PM_SECURE_AES,
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PM_CLOCK_PLL_GETPARAM = 49,
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PM_REGISTER_ACCESS = 52,
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PM_EFUSE_ACCESS,
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PM_FEATURE_CHECK = 63,
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PM_API_MAX,
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};
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#define PM_SIP_SVC 0xc2000000
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#define ZYNQMP_PM_VERSION_MAJOR 1
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#define ZYNQMP_PM_VERSION_MINOR 0
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#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
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#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
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#define ZYNQMP_PM_VERSION \
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((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
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ZYNQMP_PM_VERSION_MINOR)
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#define ZYNQMP_PM_VERSION_INVALID ~0
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#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
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unsigned int zynqmp_firmware_version(void);
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void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
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int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
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u32 arg3, u32 *ret_payload);
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#endif /* _ZYNQMP_FIRMWARE_H_ */
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