mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 05:36:17 +09:00
da90d4ce38
Generalized misuse of ble within relocation and bss
initialization loops caused one iteration too many.
Instead of ble ('branch if lower or equal'), use
blo ('branch if lower').
While we're at it, fix all 'addreee' typos.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
807 lines
17 KiB
ArmAsm
807 lines
17 KiB
ArmAsm
/* vi: set ts=8 sw=8 noet: */
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/*
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* u-boot - Startup Code for XScale IXP
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*
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* Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
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*
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* Based on startup code example contained in the
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* Intel IXP4xx Programmer's Guide and past u-boot Start.S
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* samples.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/ixp425.h>
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#define MMU_Control_M 0x001 /* Enable MMU */
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#define MMU_Control_A 0x002 /* Enable address alignment faults */
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#define MMU_Control_C 0x004 /* Enable cache */
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#define MMU_Control_W 0x008 /* Enable write-buffer */
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#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
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#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
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#define MMU_Control_L 0x040 /* Compatability: */
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#define MMU_Control_B 0x080 /* Enable Big-Endian */
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#define MMU_Control_S 0x100 /* Enable system protection */
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#define MMU_Control_R 0x200 /* Enable ROM protection */
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#define MMU_Control_I 0x1000 /* Enable Instruction cache */
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#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
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#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
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/*
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* Macro definitions
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*/
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/* Delay a bit */
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.macro DELAY_FOR cycles, reg0
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ldr \reg0, =\cycles
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subs \reg0, \reg0, #1
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subne pc, pc, #0xc
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.endm
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/* wait for coprocessor write complete */
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.macro CPWAIT reg
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mrc p15,0,\reg,c2,c0,0
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mov \reg,\reg
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sub pc,pc,#4
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.endm
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.globl _start
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_start: b reset
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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.balignl 16,0xdeadbeef
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/*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* - relocate armboot to ram
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* - setup stack
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* - jump to second stage
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*/
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.globl _TEXT_BASE
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_TEXT_BASE:
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.word TEXT_BASE
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#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
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.globl _armboot_start
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_armboot_start:
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.word _start
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#endif
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/*
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* These are defined in the board-specific linker script.
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word _end
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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.globl _datarel_start
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_datarel_start:
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.word __datarel_start
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.globl _datarelrolocal_start
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_datarelrolocal_start:
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.word __datarelrolocal_start
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.globl _datarellocal_start
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_datarellocal_start:
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.word __datarellocal_start
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.globl _datarelro_start
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_datarelro_start:
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.word __datarelro_start
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.globl _got_start
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_got_start:
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.word __got_start
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.globl _got_end
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_got_end:
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.word __got_end
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/*
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* the actual reset code
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*/
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reset:
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/* disable mmu, set big-endian */
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mov r0, #0xf8
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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/* invalidate I & D caches & BTB */
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mcr p15, 0, r0, c7, c7, 0
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CPWAIT r0
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/* invalidate I & Data TLB */
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mcr p15, 0, r0, c8, c7, 0
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CPWAIT r0
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/* drain write and fill buffers */
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mcr p15, 0, r0, c7, c10, 4
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CPWAIT r0
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/* disable write buffer coalescing */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #1
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mcr p15, 0, r0, c1, c0, 1
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CPWAIT r0
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/* set EXP CS0 to the optimum timing */
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ldr r1, =CONFIG_SYS_EXP_CS0
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ldr r2, =IXP425_EXP_CS0
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str r1, [r2]
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/* make sure flash is visible at 0 */
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#if 0
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ldr r2, =IXP425_EXP_CFG0
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ldr r1, [r2]
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orr r1, r1, #0x80000000
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str r1, [r2]
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#endif
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mov r1, #CONFIG_SYS_SDR_CONFIG
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ldr r2, =IXP425_SDR_CONFIG
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str r1, [r2]
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/* disable refresh cycles */
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mov r1, #0
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ldr r3, =IXP425_SDR_REFRESH
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str r1, [r3]
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/* send nop command */
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mov r1, #3
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ldr r4, =IXP425_SDR_IR
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str r1, [r4]
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DELAY_FOR 0x4000, r0
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/* set SDRAM internal refresh val */
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ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
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str r1, [r3]
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DELAY_FOR 0x4000, r0
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/* send precharge-all command to close all open banks */
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mov r1, #2
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str r1, [r4]
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DELAY_FOR 0x4000, r0
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/* provide 8 auto-refresh cycles */
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mov r1, #4
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mov r5, #8
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111: str r1, [r4]
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DELAY_FOR 0x100, r0
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subs r5, r5, #1
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bne 111b
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/* set mode register in sdram */
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mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
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str r1, [r4]
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DELAY_FOR 0x4000, r0
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/* send normal operation command */
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mov r1, #6
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str r1, [r4]
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DELAY_FOR 0x4000, r0
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/* copy */
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mov r0, #0
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mov r4, r0
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add r2, r0, #CONFIG_SYS_MONITOR_LEN
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mov r1, #0x10000000
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mov r5, r1
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30:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r0, r2
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bne 30b
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/* invalidate I & D caches & BTB */
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mcr p15, 0, r0, c7, c7, 0
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CPWAIT r0
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/* invalidate I & Data TLB */
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mcr p15, 0, r0, c8, c7, 0
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CPWAIT r0
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/* drain write and fill buffers */
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mcr p15, 0, r0, c7, c10, 4
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CPWAIT r0
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/* move flash to 0x50000000 */
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ldr r2, =IXP425_EXP_CFG0
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ldr r1, [r2]
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bic r1, r1, #0x80000000
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str r1, [r2]
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nop
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nop
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nop
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nop
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nop
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nop
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/* invalidate I & Data TLB */
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mcr p15, 0, r0, c8, c7, 0
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CPWAIT r0
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/* enable I cache */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #MMU_Control_I
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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mrs r0,cpsr /* set the cpu to SVC32 mode */
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bic r0,r0,#0x1f /* (superviser mode, M=10011) */
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orr r0,r0,#0x13
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msr cpsr,r0
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/* Set stackpointer in internal RAM to call board_init_f */
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call_board_init_f:
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ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
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ldr r0,=0x00000000
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bl board_init_f
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/*------------------------------------------------------------------------------*/
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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*/
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.globl relocate_code
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relocate_code:
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mov r4, r0 /* save addr_sp */
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mov r5, r1 /* save addr of gd */
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mov r6, r2 /* save addr of destination */
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mov r7, r2 /* save addr of destination */
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/* Set up the stack */
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stack_setup:
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mov sp, r4
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adr r0, _start
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ldr r2, _TEXT_BASE
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ldr r3, _bss_start
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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cmp r0, r6
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beq clear_bss
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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copy_loop:
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ldmia r0!, {r9-r10} /* copy from source address [r0] */
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stmia r6!, {r9-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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blo copy_loop
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#ifndef CONFIG_PRELOADER
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/* fix got entries */
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ldr r1, _TEXT_BASE /* Text base */
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mov r0, r7 /* reloc addr */
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ldr r2, _got_start /* addr in Flash */
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ldr r3, _got_end /* addr in Flash */
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sub r3, r3, r1
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add r3, r3, r0
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sub r2, r2, r1
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add r2, r2, r0
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fixloop:
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ldr r4, [r2]
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sub r4, r4, r1
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add r4, r4, r0
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str r4, [r2]
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add r2, r2, #4
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cmp r2, r3
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bne fixloop
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#endif
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#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
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clear_bss:
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#ifndef CONFIG_PRELOADER
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ldr r0, _bss_start
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ldr r1, _bss_end
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ldr r3, _TEXT_BASE /* Text base */
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mov r4, r7 /* reloc addr */
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sub r0, r0, r3
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add r0, r0, r4
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sub r1, r1, r3
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add r1, r1, r4
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mov r2, #0x00000000 /* clear */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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bne clbss_l
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bl coloured_LED_init
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bl red_LED_on
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#endif
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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ldr r0, _TEXT_BASE
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ldr r2, _board_init_r
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sub r2, r2, r0
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add r2, r2, r7 /* position from board_init_r in RAM */
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/* setup parameters for board_init_r */
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mov r0, r5 /* gd_t */
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mov r1, r7 /* dest_addr */
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/* jump to it ... */
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mov lr, r2
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mov pc, lr
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_board_init_r: .word board_init_r
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#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
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/****************************************************************************/
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/* */
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/* the actual reset code */
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/* */
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/****************************************************************************/
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reset:
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/* disable mmu, set big-endian */
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mov r0, #0xf8
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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/* invalidate I & D caches & BTB */
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mcr p15, 0, r0, c7, c7, 0
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CPWAIT r0
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/* invalidate I & Data TLB */
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mcr p15, 0, r0, c8, c7, 0
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CPWAIT r0
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/* drain write and fill buffers */
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mcr p15, 0, r0, c7, c10, 4
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CPWAIT r0
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/* disable write buffer coalescing */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #1
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mcr p15, 0, r0, c1, c0, 1
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CPWAIT r0
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/* set EXP CS0 to the optimum timing */
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ldr r1, =CONFIG_SYS_EXP_CS0
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ldr r2, =IXP425_EXP_CS0
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str r1, [r2]
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/* make sure flash is visible at 0 */
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#if 0
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ldr r2, =IXP425_EXP_CFG0
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ldr r1, [r2]
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orr r1, r1, #0x80000000
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str r1, [r2]
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#endif
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mov r1, #CONFIG_SYS_SDR_CONFIG
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ldr r2, =IXP425_SDR_CONFIG
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str r1, [r2]
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/* disable refresh cycles */
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mov r1, #0
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ldr r3, =IXP425_SDR_REFRESH
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str r1, [r3]
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/* send nop command */
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mov r1, #3
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ldr r4, =IXP425_SDR_IR
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str r1, [r4]
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DELAY_FOR 0x4000, r0
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/* set SDRAM internal refresh val */
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ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
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str r1, [r3]
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DELAY_FOR 0x4000, r0
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/* send precharge-all command to close all open banks */
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mov r1, #2
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str r1, [r4]
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DELAY_FOR 0x4000, r0
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/* provide 8 auto-refresh cycles */
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mov r1, #4
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mov r5, #8
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111: str r1, [r4]
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DELAY_FOR 0x100, r0
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subs r5, r5, #1
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bne 111b
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/* set mode register in sdram */
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mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
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str r1, [r4]
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DELAY_FOR 0x4000, r0
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/* send normal operation command */
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mov r1, #6
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str r1, [r4]
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DELAY_FOR 0x4000, r0
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/* copy */
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mov r0, #0
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mov r4, r0
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add r2, r0, #CONFIG_SYS_MONITOR_LEN
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mov r1, #0x10000000
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mov r5, r1
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30:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r0, r2
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bne 30b
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/* invalidate I & D caches & BTB */
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mcr p15, 0, r0, c7, c7, 0
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CPWAIT r0
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/* invalidate I & Data TLB */
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mcr p15, 0, r0, c8, c7, 0
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CPWAIT r0
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/* drain write and fill buffers */
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mcr p15, 0, r0, c7, c10, 4
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CPWAIT r0
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/* move flash to 0x50000000 */
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ldr r2, =IXP425_EXP_CFG0
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ldr r1, [r2]
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bic r1, r1, #0x80000000
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str r1, [r2]
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nop
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nop
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nop
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nop
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nop
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nop
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/* invalidate I & Data TLB */
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mcr p15, 0, r0, c8, c7, 0
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CPWAIT r0
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/* enable I cache */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #MMU_Control_I
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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|
|
mrs r0,cpsr /* set the cpu to SVC32 mode */
|
|
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
|
|
orr r0,r0,#0x13
|
|
msr cpsr,r0
|
|
|
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
|
relocate: /* relocate U-Boot to RAM */
|
|
adr r0, _start /* r0 <- current position of code */
|
|
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
|
|
cmp r0, r1 /* don't reloc during debug */
|
|
beq stack_setup
|
|
|
|
ldr r2, _armboot_start
|
|
ldr r3, _bss_start
|
|
sub r2, r3, r2 /* r2 <- size of armboot */
|
|
add r2, r0, r2 /* r2 <- source end address */
|
|
|
|
copy_loop:
|
|
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
|
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
|
cmp r0, r2 /* until source end address [r2] */
|
|
blo copy_loop
|
|
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
|
|
|
|
/* Set up the stack */
|
|
stack_setup:
|
|
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
|
|
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
|
|
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
|
|
#ifdef CONFIG_USE_IRQ
|
|
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
|
|
#endif
|
|
sub sp, r0, #12 /* leave 3 words for abort-stack */
|
|
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
|
|
|
|
clear_bss:
|
|
ldr r0, _bss_start /* find start of bss segment */
|
|
ldr r1, _bss_end /* stop here */
|
|
mov r2, #0x00000000 /* clear */
|
|
|
|
clbss_l:str r2, [r0] /* clear loop... */
|
|
add r0, r0, #4
|
|
cmp r0, r1
|
|
blo clbss_l
|
|
|
|
ldr pc, _start_armboot
|
|
|
|
_start_armboot: .word start_armboot
|
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
|
|
|
|
|
/****************************************************************************/
|
|
/* */
|
|
/* Interrupt handling */
|
|
/* */
|
|
/****************************************************************************/
|
|
|
|
/* IRQ stack frame */
|
|
|
|
#define S_FRAME_SIZE 72
|
|
|
|
#define S_OLD_R0 68
|
|
#define S_PSR 64
|
|
#define S_PC 60
|
|
#define S_LR 56
|
|
#define S_SP 52
|
|
|
|
#define S_IP 48
|
|
#define S_FP 44
|
|
#define S_R10 40
|
|
#define S_R9 36
|
|
#define S_R8 32
|
|
#define S_R7 28
|
|
#define S_R6 24
|
|
#define S_R5 20
|
|
#define S_R4 16
|
|
#define S_R3 12
|
|
#define S_R2 8
|
|
#define S_R1 4
|
|
#define S_R0 0
|
|
|
|
#define MODE_SVC 0x13
|
|
|
|
/* use bad_save_user_regs for abort/prefetch/undef/swi ... */
|
|
|
|
.macro bad_save_user_regs
|
|
sub sp, sp, #S_FRAME_SIZE
|
|
stmia sp, {r0 - r12} /* Calling r0-r12 */
|
|
add r8, sp, #S_PC
|
|
|
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
|
ldr r2, _armboot_start
|
|
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
|
#else
|
|
ldr r2, IRQ_STACK_START_IN
|
|
#endif
|
|
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
|
|
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
|
|
|
|
add r5, sp, #S_SP
|
|
mov r1, lr
|
|
stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
|
|
mov r0, sp
|
|
.endm
|
|
|
|
|
|
/* use irq_save_user_regs / irq_restore_user_regs for */
|
|
/* IRQ/FIQ handling */
|
|
|
|
.macro irq_save_user_regs
|
|
sub sp, sp, #S_FRAME_SIZE
|
|
stmia sp, {r0 - r12} /* Calling r0-r12 */
|
|
add r8, sp, #S_PC
|
|
stmdb r8, {sp, lr}^ /* Calling SP, LR */
|
|
str lr, [r8, #0] /* Save calling PC */
|
|
mrs r6, spsr
|
|
str r6, [r8, #4] /* Save CPSR */
|
|
str r0, [r8, #8] /* Save OLD_R0 */
|
|
mov r0, sp
|
|
.endm
|
|
|
|
.macro irq_restore_user_regs
|
|
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
|
mov r0, r0
|
|
ldr lr, [sp, #S_PC] @ Get PC
|
|
add sp, sp, #S_FRAME_SIZE
|
|
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
|
.endm
|
|
|
|
.macro get_bad_stack
|
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
|
ldr r13, _armboot_start @ setup our mode stack
|
|
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
|
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
|
#else
|
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
|
#endif
|
|
|
|
str lr, [r13] @ save caller lr / spsr
|
|
mrs lr, spsr
|
|
str lr, [r13, #4]
|
|
|
|
mov r13, #MODE_SVC @ prepare SVC-Mode
|
|
msr spsr_c, r13
|
|
mov lr, pc
|
|
movs pc, lr
|
|
.endm
|
|
|
|
.macro get_irq_stack @ setup IRQ stack
|
|
ldr sp, IRQ_STACK_START
|
|
.endm
|
|
|
|
.macro get_fiq_stack @ setup FIQ stack
|
|
ldr sp, FIQ_STACK_START
|
|
.endm
|
|
|
|
|
|
/****************************************************************************/
|
|
/* */
|
|
/* exception handlers */
|
|
/* */
|
|
/****************************************************************************/
|
|
|
|
.align 5
|
|
undefined_instruction:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_undefined_instruction
|
|
|
|
.align 5
|
|
software_interrupt:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_software_interrupt
|
|
|
|
.align 5
|
|
prefetch_abort:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_prefetch_abort
|
|
|
|
.align 5
|
|
data_abort:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_data_abort
|
|
|
|
.align 5
|
|
not_used:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_not_used
|
|
|
|
#ifdef CONFIG_USE_IRQ
|
|
|
|
.align 5
|
|
irq:
|
|
get_irq_stack
|
|
irq_save_user_regs
|
|
bl do_irq
|
|
irq_restore_user_regs
|
|
|
|
.align 5
|
|
fiq:
|
|
get_fiq_stack
|
|
irq_save_user_regs /* someone ought to write a more */
|
|
bl do_fiq /* effiction fiq_save_user_regs */
|
|
irq_restore_user_regs
|
|
|
|
#else
|
|
|
|
.align 5
|
|
irq:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_irq
|
|
|
|
.align 5
|
|
fiq:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_fiq
|
|
|
|
#endif
|
|
|
|
/****************************************************************************/
|
|
/* */
|
|
/* Reset function: Use Watchdog to reset */
|
|
/* */
|
|
/****************************************************************************/
|
|
|
|
.align 5
|
|
.globl reset_cpu
|
|
|
|
reset_cpu:
|
|
ldr r1, =0x482e
|
|
ldr r2, =IXP425_OSWK
|
|
str r1, [r2]
|
|
ldr r1, =0x0fff
|
|
ldr r2, =IXP425_OSWT
|
|
str r1, [r2]
|
|
ldr r1, =0x5
|
|
ldr r2, =IXP425_OSWE
|
|
str r1, [r2]
|
|
b reset_endless
|
|
|
|
|
|
reset_endless:
|
|
|
|
b reset_endless
|
|
|
|
#ifdef CONFIG_USE_IRQ
|
|
|
|
.LC0: .word loops_per_jiffy
|
|
|
|
/*
|
|
* 0 <= r0 <= 2000
|
|
*/
|
|
.globl __udelay
|
|
__udelay:
|
|
mov r2, #0x6800
|
|
orr r2, r2, #0x00db
|
|
mul r0, r2, r0
|
|
ldr r2, .LC0
|
|
ldr r2, [r2] @ max = 0x0fffffff
|
|
mov r0, r0, lsr #11 @ max = 0x00003fff
|
|
mov r2, r2, lsr #11 @ max = 0x0003ffff
|
|
mul r0, r2, r0 @ max = 2^32-1
|
|
movs r0, r0, lsr #6
|
|
|
|
delay_loop:
|
|
subs r0, r0, #1
|
|
bne delay_loop
|
|
mov pc, lr
|
|
|
|
#endif /* CONFIG_USE_IRQ */
|