mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 05:36:17 +09:00
92cb207af1
SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
48 lines
655 B
Plaintext
48 lines
655 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com>
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*/
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#include "rk3399-u-boot.dtsi"
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#include "rk3399-sdram-lpddr4-100.dtsi"
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/ {
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc;
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};
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config {
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u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
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};
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};
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&i2c0 {
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u-boot,dm-pre-reloc;
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};
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&rk808 {
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u-boot,dm-pre-reloc;
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};
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&rng {
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status = "okay";
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};
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&sdhci {
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max-frequency = <25000000>;
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u-boot,dm-pre-reloc;
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};
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&sdmmc {
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max-frequency = <20000000>;
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u-boot,dm-pre-reloc;
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};
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&spiflash {
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u-boot,dm-pre-reloc;
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};
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&vdd_log {
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regulator-init-microvolt = <950000>;
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};
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