mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
f86ed75059
Move Stratix10 and Agilex SPL common code to spl_soc64.c. We are in preparation for new n5x device support. No functional change in this patch. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
95 lines
2.1 KiB
C
95 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <common.h>
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#include <debug_uart.h>
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#include <image.h>
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#include <spl.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/firewall.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <watchdog.h>
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#include <dm/uclass.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_init_f(ulong dummy)
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{
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const struct cm_config *cm_default_cfg = cm_get_default_config();
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int ret;
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ret = spl_early_init();
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if (ret)
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hang();
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socfpga_get_managers_addr();
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/* Ensure watchdog is paused when debugging is happening */
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writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
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socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
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#ifdef CONFIG_HW_WATCHDOG
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/* Enable watchdog before initializing the HW */
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
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hw_watchdog_init();
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#endif
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/* ensure all processors are not released prior Linux boot */
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writeq(0, CPU_RELEASE_ADDR);
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socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
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timer_init();
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sysmgr_pinmux_init();
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/* configuring the HPS clocks */
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cm_basic_init(cm_default_cfg);
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#ifdef CONFIG_DEBUG_UART
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socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
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debug_uart_init();
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#endif
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preloader_console_init();
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print_reset_info();
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cm_print_clock_quick_summary();
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firewall_setup();
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/* disable ocram security at CCU for non secure access */
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clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
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CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
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CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
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#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
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struct udevice *dev;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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hang();
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}
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#endif
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mbox_init();
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#ifdef CONFIG_CADENCE_QSPI
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mbox_qspi_open();
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#endif
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}
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