mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
404a98b0a4
Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
33 lines
868 B
C
33 lines
868 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
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*/
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#ifndef _CLOCK_MANAGER_H_
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#define _CLOCK_MANAGER_H_
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phys_addr_t socfpga_get_clkmgr_addr(void);
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#ifndef __ASSEMBLY__
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void cm_wait_for_lock(u32 mask);
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int cm_wait_for_fsm(void);
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void cm_print_clock_quick_summary(void);
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unsigned int cm_get_qspi_controller_clk_hz(void);
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#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
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int cm_set_qspi_controller_clk_hz(u32 clk_hz);
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#endif
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#endif
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#include <asm/arch/clock_manager_gen5.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#include <asm/arch/clock_manager_arria10.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
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#include <asm/arch/clock_manager_s10.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
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#include <asm/arch/clock_manager_agilex.h>
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#endif
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#endif /* _CLOCK_MANAGER_H_ */
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