mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 13:16:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
387 lines
11 KiB
C
387 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-vf610.h>
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#include <asm/arch/ddrmc-vf610.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
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#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
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static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
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/* levelling */
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{ DDRMC_CR97_WRLVL_EN, 97 },
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{ DDRMC_CR98_WRLVL_DL_0(0), 98 },
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{ DDRMC_CR99_WRLVL_DL_1(0), 99 },
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{ DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
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{ DDRMC_CR105_RDLVL_DL_0(0), 105 },
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{ DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
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{ DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
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/* AXI */
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{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
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{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
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{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
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DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
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{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
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DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
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{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
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DDRMC_CR122_AXI0_PRIRLX(100), 122 },
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{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
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DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
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{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
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{ DDRMC_CR126_PHY_RDLAT(8), 126 },
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{ DDRMC_CR132_WRLAT_ADJ(5) |
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DDRMC_CR132_RDLAT_ADJ(6), 132 },
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{ DDRMC_CR137_PHYCTL_DL(2), 137 },
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{ DDRMC_CR138_PHY_WRLV_MXDL(256) |
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DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
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{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
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DDRMC_CR139_PHY_WRLV_DLL(3) |
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DDRMC_CR139_PHY_WRLV_EN(3), 139 },
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{ DDRMC_CR140_PHY_WRLV_WW(64), 140 },
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{ DDRMC_CR143_RDLV_GAT_MXDL(1536) |
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DDRMC_CR143_RDLV_MXDL(128), 143 },
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{ DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
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DDRMC_CR144_PHY_RDLV_DLL(3) |
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DDRMC_CR144_PHY_RDLV_EN(3), 144 },
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{ DDRMC_CR145_PHY_RDLV_RR(64), 145 },
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{ DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
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{ DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
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{ DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
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{ DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
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DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
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{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
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DDRMC_CR154_PAD_ZQ_MODE(1) |
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DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
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DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
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{ DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
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{ DDRMC_CR158_TWR(6), 158 },
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{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
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DDRMC_CR161_TODTH_WR(2), 161 },
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/* end marker */
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{ 0, -1 }
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};
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int dram_init(void)
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{
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static const struct ddr3_jedec_timings timings = {
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.tinit = 5,
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.trst_pwron = 80000,
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.cke_inactive = 200000,
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.wrlat = 5,
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.caslat_lin = 12,
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.trc = 21,
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.trrd = 4,
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.tccd = 4,
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.tbst_int_interval = 0,
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.tfaw = 20,
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.trp = 6,
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.twtr = 4,
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.tras_min = 15,
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.tmrd = 4,
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.trtp = 4,
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.tras_max = 28080,
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.tmod = 12,
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.tckesr = 4,
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.tcke = 3,
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.trcd_int = 6,
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.tras_lockout = 0,
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.tdal = 12,
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.bstlen = 3,
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.tdll = 512,
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.trp_ab = 6,
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.tref = 3120,
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.trfc = 44,
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.tref_int = 0,
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.tpdex = 3,
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.txpdll = 10,
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.txsnr = 48,
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.txsr = 468,
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.cksrx = 5,
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.cksre = 5,
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.freq_chg_en = 0,
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.zqcl = 256,
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.zqinit = 512,
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.zqcs = 64,
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.ref_per_zq = 64,
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.zqcs_rotate = 0,
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.aprebit = 10,
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.cmd_age_cnt = 64,
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.age_cnt = 64,
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.q_fullness = 7,
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.odt_rd_mapcs0 = 0,
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.odt_wr_mapcs0 = 1,
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.wlmrd = 40,
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.wldqsen = 25,
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};
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ddrmc_setup_iomux(NULL, 0);
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ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart1_pads[] = {
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NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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static void setup_iomux_enet(void)
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{
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static const iomux_v3_cfg_t enet0_pads[] = {
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NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
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}
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static void setup_iomux_i2c(void)
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{
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static const iomux_v3_cfg_t i2c0_pads[] = {
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VF610_PAD_PTB14__I2C0_SCL,
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VF610_PAD_PTB15__I2C0_SDA,
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};
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imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
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}
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#ifdef CONFIG_NAND_VF610_NFC
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static void setup_iomux_nfc(void)
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{
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static const iomux_v3_cfg_t nfc_pads[] = {
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VF610_PAD_PTD31__NF_IO15,
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VF610_PAD_PTD30__NF_IO14,
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VF610_PAD_PTD29__NF_IO13,
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VF610_PAD_PTD28__NF_IO12,
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VF610_PAD_PTD27__NF_IO11,
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VF610_PAD_PTD26__NF_IO10,
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VF610_PAD_PTD25__NF_IO9,
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VF610_PAD_PTD24__NF_IO8,
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VF610_PAD_PTD23__NF_IO7,
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VF610_PAD_PTD22__NF_IO6,
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VF610_PAD_PTD21__NF_IO5,
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VF610_PAD_PTD20__NF_IO4,
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VF610_PAD_PTD19__NF_IO3,
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VF610_PAD_PTD18__NF_IO2,
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VF610_PAD_PTD17__NF_IO1,
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VF610_PAD_PTD16__NF_IO0,
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VF610_PAD_PTB24__NF_WE_B,
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VF610_PAD_PTB25__NF_CE0_B,
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VF610_PAD_PTB27__NF_RE_B,
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VF610_PAD_PTC26__NF_RB_B,
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VF610_PAD_PTC27__NF_ALE,
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VF610_PAD_PTC28__NF_CLE
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};
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imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
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}
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#endif
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static void setup_iomux_qspi(void)
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{
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static const iomux_v3_cfg_t qspi0_pads[] = {
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VF610_PAD_PTD0__QSPI0_A_QSCK,
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VF610_PAD_PTD1__QSPI0_A_CS0,
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VF610_PAD_PTD2__QSPI0_A_DATA3,
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VF610_PAD_PTD3__QSPI0_A_DATA2,
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VF610_PAD_PTD4__QSPI0_A_DATA1,
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VF610_PAD_PTD5__QSPI0_A_DATA0,
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VF610_PAD_PTD7__QSPI0_B_QSCK,
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VF610_PAD_PTD8__QSPI0_B_CS0,
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VF610_PAD_PTD9__QSPI0_B_DATA3,
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VF610_PAD_PTD10__QSPI0_B_DATA2,
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VF610_PAD_PTD11__QSPI0_B_DATA1,
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VF610_PAD_PTD12__QSPI0_B_DATA0,
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};
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imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[1] = {
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{ESDHC1_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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/* eSDHC1 is always present */
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return 1;
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}
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int board_mmc_init(bd_t *bis)
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{
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static const iomux_v3_cfg_t esdhc1_pads[] = {
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NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
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NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
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};
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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imx_iomux_v3_setup_multiple_pads(
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esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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}
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#endif
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static void clock_init(void)
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{
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struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
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struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
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clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
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CCM_CCGR0_UART1_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
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CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
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CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
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CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
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CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
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CCM_CCGR2_QSPI0_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
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CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
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CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
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CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
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CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
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CCM_CCGR7_SDHC1_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
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CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
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clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
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CCM_CCGR10_NFC_CTRL_MASK);
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clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
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ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
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clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
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ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
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clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
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CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
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clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
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CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
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CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
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CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
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CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
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CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
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CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
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clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
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CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
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CCM_CACRR_ARM_CLK_DIV(0));
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clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
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CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
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CCM_CSCMR1_NFC_CLK_SEL(0));
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clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
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CCM_CSCDR1_RMII_CLK_EN);
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clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
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CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
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CCM_CSCDR2_NFC_EN);
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clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
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CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
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CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
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CCM_CSCDR3_NFC_PRE_DIV(5));
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clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
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CCM_CSCMR2_RMII_CLK_SEL(0));
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}
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static void mscm_init(void)
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{
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struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
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int i;
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for (i = 0; i < MSCM_IRSPRC_NUM; i++)
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writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_early_init_f(void)
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{
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clock_init();
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mscm_init();
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setup_iomux_uart();
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setup_iomux_enet();
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setup_iomux_i2c();
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setup_iomux_qspi();
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#ifdef CONFIG_NAND_VF610_NFC
|
|
setup_iomux_nfc();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
|
|
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
/*
|
|
* Enable external 32K Oscillator
|
|
*
|
|
* The internal clock experiences significant drift
|
|
* so we must use the external oscillator in order
|
|
* to maintain correct time in the hwclock
|
|
*/
|
|
setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: vf610twr\n");
|
|
|
|
return 0;
|
|
}
|