mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
91ee54741e
The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Matteo Ghidoni <matteo.ghidoni@hitachi-powergrids.com> Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
161 lines
3.1 KiB
C
161 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 Hitachi Power Grids. All rights reserved.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <hwconfig.h>
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#include <mmc.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <fsl_ifc.h>
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#include <fsl_immap.h>
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#include <netdev.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <fsl_sec.h>
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#include <fsl_devdis.h>
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#include <fsl_ddr.h>
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#include <spl.h>
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#include <fdt_support.h>
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#include <fsl_qe.h>
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#include <fsl_validate.h>
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#include "../common/common.h"
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#include "../common/qrio.h"
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DECLARE_GLOBAL_DATA_PTR;
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static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
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int checkboard(void)
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{
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show_qrio();
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return 0;
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}
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int dram_init(void)
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{
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return fsl_initdram();
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}
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
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/* Disable unused MCK1 */
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setbits_be32(&gur->ddrclkdr, 2);
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/* IFC Global Configuration */
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setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
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setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) |
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IFC_CCR_INV_CLK_EN);
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/* clear BD & FR bits for BE BD's and frame data */
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clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
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init_early_memctl_regs();
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/* QRIO Configuration */
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qrio_uprstreq(UPREQ_CORE_RST);
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if (IS_ENABLED(CONFIG_TARGET_PG_WCOM_SELI8)) {
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qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_LIU_RST, true);
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qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_PAXK_RST, true);
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qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
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qrio_prst(KM_DBG_ETH_RST, false, false);
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}
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i2c_deblock_gpio_cfg();
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arch_soc_init();
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return 0;
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}
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int board_init(void)
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{
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if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315))
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erratum_a010315();
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fsl_serdes_init();
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ls102xa_smmu_stream_id_init();
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u_qe_init();
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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int misc_init_r(void)
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{
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if (IS_ENABLED(CONFIG_FSL_DEVICE_DISABLE))
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device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
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ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
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CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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ft_cpu_setup(blob, bd);
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if (IS_ENABLED(CONFIG_PCI))
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ft_pci_setup(blob, bd);
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return 0;
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}
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u8 flash_read8(void *addr)
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{
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return __raw_readb(addr + 1);
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}
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void flash_write16(u16 val, void *addr)
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{
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u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
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__raw_writew(shftval, addr);
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}
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u16 flash_read16(void *addr)
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{
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u16 val = __raw_readw(addr);
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
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}
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int hush_init_var(void)
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{
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ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
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return 0;
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}
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int last_stage_init(void)
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{
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set_km_env();
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return 0;
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}
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