u-boot-brain/cpu/mpc86xx
Haiying Wang 9964a4dd0d Set Rev 2.x 86xx PIC in mixed mode.
Prevent false interrupt from hanging Linux as MSR[EE] is set
to enable interrupts by changing the PIC out of the default
pass through mode into mixed mode.

Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-03-22 11:02:35 -05:00
..
cache.S Remove L2 Cache invalidate polling. 2006-05-19 13:54:02 -05:00
config.mk Review cleanups. 2006-05-31 14:01:32 -05:00
cpu_init.c Remove trailing empty lines. 2006-08-29 11:05:09 -05:00
cpu.c Handle 86xx SVR values according to the new Reference Manual. 2006-09-14 08:40:36 -05:00
interrupts.c Set Rev 2.x 86xx PIC in mixed mode. 2007-03-22 11:02:35 -05:00
Makefile Fix "ar" flags in some Makefiles to allow for silent "make -s" 2006-10-27 11:55:21 +02:00
pci.c General indent and whitespace cleanups. 2006-08-22 12:06:18 -05:00
pcie_indirect.c General indent and whitespace cleanups. 2006-08-22 12:06:18 -05:00
resetvec.S Initial support for MPC8641 HPCN board. 2006-04-26 17:58:56 -05:00
spd_sdram.c Add support for 8641 Rev 2 silicon. 2007-03-22 11:02:34 -05:00
speed.c General indent and whitespace cleanups. 2006-08-22 12:06:18 -05:00
start.S Code cleanup 2006-10-24 15:32:57 +02:00
traps.c General indent and whitespace cleanups. 2006-08-22 12:06:18 -05:00