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https://github.com/brain-hackers/u-boot-brain
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72a087e047
Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
114 lines
2.6 KiB
ArmAsm
114 lines
2.6 KiB
ArmAsm
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/sysreg.h>
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#ifndef PART_SPECIFIC_BOOTSTRAP
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# define PART_SPECIFIC_BOOTSTRAP
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#endif
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#define SYSREG_MMUCR_I_OFFSET 2
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#define SYSREG_MMUCR_S_OFFSET 4
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#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
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#define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE) \
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| SYSREG_BIT(FE) | SYSREG_BIT(RE) \
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| SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
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.text
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.global _start
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_start:
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PART_SPECIFIC_BOOTSTRAP
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/* Reset the Status Register */
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mov r0, lo(SR_INIT)
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orh r0, hi(SR_INIT)
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mtsr SYSREG_SR, r0
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/* Reset CPUCR and invalidate the BTB */
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mov r2, CPUCR_INIT
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mtsr SYSREG_CPUCR, r2
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/* Flush the caches */
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mov r1, 0
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cache r1[4], 8
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cache r1[0], 0
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sync 0
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/* Reset the MMU to default settings */
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mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
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mtsr SYSREG_MMUCR, r0
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/* Internal RAM should not need any initialization. We might
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have to initialize external RAM here if the part doesn't
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have internal RAM (or we may use the data cache) */
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/* Jump to cacheable segment */
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lddpc pc, 1f
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.align 2
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1: .long 2f
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2: lddpc sp, sp_init
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/*
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* Relocate the data section and initialize .bss. Everything
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* is guaranteed to be at least doubleword aligned by the
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* linker script.
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*/
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lddpc r12, .Ldata_vma
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lddpc r11, .Ldata_lma
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lddpc r10, .Ldata_end
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sub r10, r12
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4: ld.d r8, r11++
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sub r10, 8
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st.d r12++, r8
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brne 4b
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mov r8, 0
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mov r9, 0
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lddpc r10, .Lbss_end
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sub r10, r12
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4: sub r10, 8
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st.d r12++, r8
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brne 4b
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/* Initialize the GOT pointer */
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lddpc r6, got_init
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3: rsub r6, pc
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ld.w pc, r6[start_u_boot@got]
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.align 2
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.type sp_init,@object
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sp_init:
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.long CFG_INIT_SP_ADDR
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got_init:
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.long 3b - _GLOBAL_OFFSET_TABLE_
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.Ldata_lma:
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.long __data_lma
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.Ldata_vma:
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.long _data
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.Ldata_end:
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.long _edata
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.Lbss_end:
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.long _end
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