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https://github.com/brain-hackers/u-boot-brain
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![Haavard Skinnemoen](/assets/img/avatar_default.png)
Use the MMU hardware to set up 1:1 mappings between physical and virtual addresses. This allows us to bypass the cache when accessing the flash without having to do any physical-to-virtual address mapping in the CFI driver. The virtual memory mappings are defined at compile time through a sorted array of virtual memory range objects. When a TLB miss exception happens, the exception handler does a binary search through the array until it finds a matching entry and loads it into the TLB. The u-boot image itself is covered by a fixed TLB entry which is never replaced. This makes the 'saveenv' command work again on ATNGW100 and other boards using the CFI driver, hopefully without breaking any rules. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_AVR32_ADDRSPACE_H
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#define __ASM_AVR32_ADDRSPACE_H
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#include <asm/types.h>
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/* Memory segments when segmentation is enabled */
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#define P0SEG 0x00000000
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#define P1SEG 0x80000000
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#define P2SEG 0xa0000000
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#define P3SEG 0xc0000000
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#define P4SEG 0xe0000000
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/* Returns the privileged segment base of a given address */
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#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
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/* Returns the physical address of a PnSEG (n=1,2) address */
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#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
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/*
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* Map an address to a certain privileged segment
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*/
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#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
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#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
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#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
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#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
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/* virt_to_phys will only work when address is in P1 or P2 */
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static inline unsigned long virt_to_phys(volatile void *address)
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{
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return PHYSADDR(address);
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}
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static inline void * phys_to_virt(unsigned long address)
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{
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return (void *)P1SEGADDR(address);
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}
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#define cached(addr) ((void *)P1SEGADDR(addr))
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#define uncached(addr) ((void *)P2SEGADDR(addr))
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/*
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* Given a physical address and a length, return a virtual address
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* that can be used to access the memory range with the caching
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* properties specified by "flags".
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*
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* This implementation works for memory below 512MiB (flash, etc.) as
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* well as above 3.5GiB (internal peripherals.)
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*/
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#define MAP_NOCACHE (0)
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#define MAP_WRCOMBINE (1 << 7)
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#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9))
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#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0))
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static inline void *
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map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
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{
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return (void *)paddr;
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}
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#endif /* __ASM_AVR32_ADDRSPACE_H */
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